[Intel-gfx] [PATCH] drm/i915: Increase context alignment requirement for Sandybridge

Chris Wilson chris at chris-wilson.co.uk
Tue Mar 22 14:07:24 UTC 2016

In bugzilla, there are some very weird bugs on SNB GT1 whereby the
seqno stop being written, but the GPU is otherwise functional, well the
command streamer at least! However, since the seqno were not being
updated any waits upon rendering results hung, triggering the GPU hang

I found a very similar hang when running igt/gem_exec_whisper on a SNB
GT1 and after playing around came to the conclusion that:

(a) it depends on timing, enabling debug and other slowdowns masks the

(b) it was not context size, as increasing the allocation to 128KiB made
no difference;

(c) it depended upon placement as restricting the binding to the
mappable region works;

(d) it depended upon alignment of the context binding, though the bspec
still only lists the restriction as 4k

Changing the alignment constrainst seems to be least intrusive, and
though I have not been able to reproduce this on snb-gt2 and all the
recent bugs to the best of my knowledge have been snb-gt1, it is safer
to apply the constraint to all snb. Though I am still a little wary that
is merely a side-effect that is papering over the issue (for example, it
may be placement of the context next to another object that is causng
the issue, or it may be finding the new alignment slows down context
switches enough etc).

Testcase: igt/gem_exec_whisper/render-contexts-interruptible #snb-gt1
References: (e.g.) https://bugs.freedesktop.org/show_bug.cgi?id=93262
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Cc: stable at vger.kernel.org
 drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 394e525e55f1..f0883a968e11 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -94,7 +94,7 @@
  * I've seen in a spec to date, and that was a workaround for a non-shipping
  * part. It should be safe to decrease this, but it's more future proof as is.
-#define GEN6_CONTEXT_ALIGN (64<<10)
+#define GEN6_CONTEXT_ALIGN (256<<10)
 #define GEN7_CONTEXT_ALIGN 4096
 static size_t get_context_alignment(struct drm_device *dev)

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