[Intel-gfx] [PATCH 1/2] drm/i915: Cache elsp submit register

[Tvrtko Ursulin]

On 22/03/16 17:29, Ville Syrjälä wrote:
> On Tue, Mar 22, 2016 at 05:16:52PM +0000, Tvrtko Ursulin wrote:
>> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
>>
>> Since we write four times to the same register, caching
>> the mmio register saves a tiny amount of generated code.
>
> The compiler can't figure this out on its own?

Nope, at least gcc 4.84 I am running here can't. :(

And this only solves one part of the things it can't figure out in that 
code. It still recalculates one part, can't remember which one is which 
now without revisiting the generated assembly. It used to be for times 
in a row: load register, add 0x230, displace 0x78, store[0-4]. This only 
solves the add 0x230 redundancy. But working around that would possibly 
be a bit too low level.

Regards,

Tvrtko