[Intel-gfx] [PATCH v3] drm/i915: Move execlists irq handler to a bottom half

[Chris Wilson]

On Thu, Mar 24, 2016 at 12:18:49PM +0000, Tvrtko Ursulin wrote:
>  /**
>   * intel_lrc_irq_handler() - handle Context Switch interrupts
> - * @ring: Engine Command Streamer to handle.
> + * @engine: Engine Command Streamer to handle.
>   *
>   * Check the unread Context Status Buffers and manage the submission of new
>   * contexts to the ELSP accordingly.
>   */
> -void intel_lrc_irq_handler(struct intel_engine_cs *engine)
> +void intel_lrc_irq_handler(unsigned long data)

Now should be made static.

> @@ -552,7 +551,7 @@ void intel_lrc_irq_handler(struct intel_engine_cs *engine)
>  	unsigned int csb_read = 0, i;
>  	unsigned int submit_contexts = 0;
>  
> -	spin_lock(&dev_priv->uncore.lock);
> +	spin_lock_irq(&dev_priv->uncore.lock);
>  	intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL);
>  
>  	status_pointer = I915_READ_FW(RING_CONTEXT_STATUS_PTR(engine));
> @@ -579,7 +578,7 @@ void intel_lrc_irq_handler(struct intel_engine_cs *engine)
>  				    engine->next_context_status_buffer << 8));
>  
>  	intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL);
> -	spin_unlock(&dev_priv->uncore.lock);
> +	spin_unlock_irq(&dev_priv->uncore.lock);

We actually can make this section just guarded by
intel_uncore_forcewake_get/intel_uncore_forcewake_put and drop the
explicit spin_lock_irq(uncore.lock). We know no one else can do
simultaneous access to this cacheline of mmio space (though that
shouldn't affect any of these machines!) and so can reduce the critical
section. At the cost of the extra lock/unlock though, versus the
potential for multiple cores to be reading from mmio.

> @@ -2016,6 +2015,8 @@ void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
>  	if (!intel_engine_initialized(engine))
>  		return;
>  
> +	tasklet_kill(&engine->irq_tasklet);

Imre suggested that we assert that the irq_tasklet is idle.
WARN_ON(test_bit(TASK_STATE_SCHED, &engine->irq_tasklet.state));
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre