[Intel-gfx] [PATCH i-g-t v4 4/5] tests/gem_scheduler: Add subtests to test batch priority behaviour

Derek Morton derek.j.morton at intel.com
Wed Mar 30 13:00:37 UTC 2016


Add subtests to test each ring to check batch buffers of a higher
priority will be executed before batch buffers of a lower priority.

v2: Addressed review comments from Daniele Ceraolo Spurio

v4: Changed priorities to +/-200  - Daniele Ceraolo Spurio

Signed-off-by: Derek Morton <derek.j.morton at intel.com>
---
 tests/gem_scheduler.c | 57 ++++++++++++++++++++++++++++++++++++++++++---------
 1 file changed, 47 insertions(+), 10 deletions(-)

diff --git a/tests/gem_scheduler.c b/tests/gem_scheduler.c
index 704dbb1..504607f 100644
--- a/tests/gem_scheduler.c
+++ b/tests/gem_scheduler.c
@@ -39,7 +39,8 @@
 
 IGT_TEST_DESCRIPTION("Check scheduler behaviour. Basic tests ensure independant "
                      "batch buffers of the same priority are executed in "
-                     "submission order. Read-read tests ensure "
+                     "submission order. Priority tests ensure higher priority "
+                     "batch buffers are executed first. Read-read tests ensure "
                      "batch buffers with a read dependency to the same buffer "
                      "object do not block each other. Write-write dependency "
                      "tests ensure batch buffers with a write dependency to a "
@@ -61,7 +62,7 @@ static struct ring {
 } rings[] = {
 	{ "render", I915_EXEC_RENDER, false },
 	{ "bsd",    I915_EXEC_BSD , false },
-	{ "bsd2",    I915_EXEC_BSD | 2<<13, false },
+	{ "bsd2",   I915_EXEC_BSD | 2<<13, false },
 	{ "blt",    I915_EXEC_BLT, false },
 	{ "vebox",  I915_EXEC_VEBOX, false },
 };
@@ -70,7 +71,7 @@ static struct ring {
 
 static void check_rings(int fd) {
 	int loop;
-	for (loop=0; loop < NBR_RINGS; loop++) {
+	for (loop = 0; loop < NBR_RINGS; loop++) {
 		if (gem_has_ring(fd, rings[loop].id)) {
 			if (rings[loop].id == (I915_EXEC_BSD | 2<<13)) {
 				rings[loop].exists = gem_has_bsd2(fd);
@@ -145,11 +146,23 @@ static void init_context(int *fd, drm_intel_bufmgr **bufmgr, int ringid)
 	intel_batchbuffer_free(noop_bb);
 }
 
-/* Basic test. Check batch buffers of the same priority and with no dependencies
- * are executed in the order they are submitted.
+static void set_priority(int fd, int value)
+{
+	struct local_i915_gem_context_param param;
+	param.context = 0; /* Default context */
+	param.size = 0;
+	param.param = LOCAL_CONTEXT_PARAM_PRIORITY;
+	param.value = (uint64_t)value;
+	gem_context_set_param(fd, &param);
+}
+
+/* If 'priority' is 0, check batch buffers of the same priority and with
+ * no dependencies are executed in the order they are submitted.
+ * If 'priority' is set !0, check batch buffers of higher priority are
+ * executed before batch buffers of lower priority.
  */
 #define NBR_BASIC_FDs (3)
-static void run_test_basic(int in_flight, int ringid)
+static void run_test_basic(int in_flight, int ringid, int priority)
 {
 	int fd[NBR_BASIC_FDs];
 	int loop;
@@ -169,6 +182,13 @@ static void run_test_basic(int in_flight, int ringid)
 	for (loop = 0; loop < NBR_BASIC_FDs; loop++)
 		init_context(&(fd[loop]), &(bufmgr[loop]), ringid);
 
+	/* For high priority set priority of second context to overtake first
+	 * For low priority set priority of first context to be overtaxen by second
+	 */
+	if(priority > 0)
+		set_priority(fd[2], priority);
+	else if(priority < 0)
+		set_priority(fd[1], priority);
 
 	/* Create buffer objects */
 	delay_bo = create_and_check_bo(bufmgr[0], "delay bo");
@@ -212,9 +232,14 @@ static void run_test_basic(int in_flight, int ringid)
 	igt_assert_f(igt_compare_timestamps(delay_buf[2], ts1_buf[0]),
 	             "Delay ts (0x%08" PRIx32 ") > TS1 ts (0x%08" PRIx32 ")\n",
 	             delay_buf[2], ts1_buf[0]);
-	igt_assert_f(igt_compare_timestamps(ts1_buf[0], ts2_buf[0]),
-	             "TS1 ts (0x%08" PRIx32 ") > TS2 ts (0x%08" PRIx32 ")\n",
-	             ts1_buf[0], ts2_buf[0]);
+	if(priority)
+		igt_assert_f(igt_compare_timestamps(ts2_buf[0], ts1_buf[0]),
+		             "TS2 ts (0x%08" PRIx32 ") > TS1 ts (0x%08" PRIx32 ")\n",
+		             ts2_buf[0], ts1_buf[0]);
+	else
+		igt_assert_f(igt_compare_timestamps(ts1_buf[0], ts2_buf[0]),
+		             "TS1 ts (0x%08" PRIx32 ") > TS2 ts (0x%08" PRIx32 ")\n",
+		             ts1_buf[0], ts2_buf[0]);
 
 	/* Cleanup */
 	for (loop = 0; loop < in_flight; loop++)
@@ -430,7 +455,19 @@ igt_main
 	for (loop = 0; loop < NBR_RINGS; loop++)
 		igt_subtest_f("%s-basic", rings[loop].name) {
 			gem_require_ring(fd, rings[loop].id);
-			run_test_basic(in_flight, rings[loop].id);
+			run_test_basic(in_flight, rings[loop].id, false);
+		}
+
+	for (loop = 0; loop < NBR_RINGS; loop++)
+		igt_subtest_f("%s-priority-high", rings[loop].name) {
+			gem_require_ring(fd, rings[loop].id);
+			run_test_basic(in_flight, rings[loop].id, 200);
+		}
+
+	for (loop = 0; loop < NBR_RINGS; loop++)
+		igt_subtest_f("%s-priority-low", rings[loop].name) {
+			gem_require_ring(fd, rings[loop].id);
+			run_test_basic(in_flight, rings[loop].id, -200);
 		}
 
 	for (loop = 0; loop < NBR_RINGS; loop++)
-- 
1.9.1



More information about the Intel-gfx mailing list