[Intel-gfx] [PATCH 5/5] CABC support for Panel PWM backlight control

[Jani Nikula]

From: Deepak M <m.deepak at intel.com>

In CABC (Content Adaptive Brightness Control) content grey level
scale can be increased while simultaneously decreasing
brightness of the backlight to achieve same perceived brightness.

The CABC is not standardized and panel vendors are free to follow
their implementation. The CABC implementaion here assumes that the
panels use standard SW register for control.

CABC is supported only when the PWM source for backlight is
from the panel.

v2 by Jani: rebase, renames, check cabc support earlier, etc.

Signed-off-by: Deepak M <m.deepak at intel.com>
Signed-off-by: Jani Nikula <jani.nikula at intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c               | 17 +++++++++++++++++
 drivers/gpu/drm/i915/intel_dsi.h               |  1 +
 drivers/gpu/drm/i915/intel_dsi_dcs_backlight.c | 22 ++++++++++++++++++++++
 3 files changed, 40 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 9326e9dcbe50..6982f0b7dd2d 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -1235,11 +1235,28 @@ void intel_dsi_init(struct drm_device *dev)
 			intel_dsi->dcs_backlight_ports = BIT(PORT_A) | BIT(PORT_C);
 			break;
 		}
+
+		switch (dev_priv->vbt.dsi.config->dl_dcs_cabc_ports) {
+		case DL_DCS_PORT_A:
+			intel_dsi->dcs_cabc_ports = BIT(PORT_A);
+			break;
+		case DL_DCS_PORT_C:
+			intel_dsi->dcs_cabc_ports = BIT(PORT_C);
+			break;
+		default:
+		case DL_DCS_PORT_A_AND_C:
+			intel_dsi->dcs_cabc_ports = BIT(PORT_A) | BIT(PORT_C);
+			break;
+		}
 	} else {
 		intel_dsi->ports = BIT(port);
 		intel_dsi->dcs_backlight_ports = BIT(port);
+		intel_dsi->dcs_cabc_ports = BIT(port);
 	}
 
+	if (!dev_priv->vbt.dsi.config->cabc_supported)
+		intel_dsi->dcs_cabc_ports = 0;
+
 	/* Create a DSI host (and a device) for each port. */
 	for_each_dsi_port(port, intel_dsi->ports) {
 		struct intel_dsi_host *host;
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index efb07f45316f..6d84de30f289 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -80,6 +80,7 @@ struct intel_dsi {
 	u8 dual_link;
 
 	u16 dcs_backlight_ports;
+	u16 dcs_cabc_ports;
 
 	u8 pixel_overlap;
 	u32 port_bits;
diff --git a/drivers/gpu/drm/i915/intel_dsi_dcs_backlight.c b/drivers/gpu/drm/i915/intel_dsi_dcs_backlight.c
index bcc10c105c21..9ca74e84c857 100644
--- a/drivers/gpu/drm/i915/intel_dsi_dcs_backlight.c
+++ b/drivers/gpu/drm/i915/intel_dsi_dcs_backlight.c
@@ -33,6 +33,12 @@
 #define CONTROL_DISPLAY_DD		(1 << 3)
 #define CONTROL_DISPLAY_BL		(1 << 2)
 
+#define POWER_SAVE_OFF			(0 << 0)
+#define POWER_SAVE_LOW			(1 << 0)
+#define POWER_SAVE_MEDIUM		(2 << 0)
+#define POWER_SAVE_HIGH			(3 << 0)
+#define POWER_SAVE_OUTDOOR_MODE		(4 << 0)
+
 #define PANEL_PWM_MAX_VALUE		0xFF
 
 static u32 dcs_get_backlight(struct intel_connector *connector)
@@ -79,6 +85,14 @@ static void dcs_disable_backlight(struct intel_connector *connector)
 
 	dcs_set_backlight(connector, 0);
 
+	for_each_dsi_port(port, intel_dsi->dcs_cabc_ports) {
+		u8 cabc = POWER_SAVE_OFF;
+
+		dsi_device = intel_dsi->dsi_hosts[port]->device;
+		mipi_dsi_dcs_write(dsi_device, MIPI_DCS_WRITE_POWER_SAVE,
+				   &cabc, sizeof(cabc));
+	}
+
 	for_each_dsi_port(port, intel_dsi->dcs_backlight_ports) {
 		u8 ctrl = 0;
 
@@ -120,6 +134,14 @@ static void dcs_enable_backlight(struct intel_connector *connector)
 				   &ctrl, sizeof(ctrl));
 	}
 
+	for_each_dsi_port(port, intel_dsi->dcs_cabc_ports) {
+		u8 cabc = POWER_SAVE_MEDIUM;
+
+		dsi_device = intel_dsi->dsi_hosts[port]->device;
+		mipi_dsi_dcs_write(dsi_device, MIPI_DCS_WRITE_POWER_SAVE,
+				   &cabc, sizeof(cabc));
+	}
+
 	dcs_set_backlight(connector, panel->backlight.level);
 }
 
-- 
2.1.4