[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Allow MI_LOAD_REGISTER_REG between whitelisted registers.
Patchwork
patchwork at emeril.freedesktop.org
Thu May 5 10:42:09 UTC 2016
== Series Details ==
Series: drm/i915: Allow MI_LOAD_REGISTER_REG between whitelisted registers.
URL : https://patchwork.freedesktop.org/series/6774/
State : success
== Summary ==
Series 6774v1 drm/i915: Allow MI_LOAD_REGISTER_REG between whitelisted registers.
http://patchwork.freedesktop.org/api/1.0/series/6774/revisions/1/mbox/
Test gem_exec_suspend:
Subgroup basic-s4:
fail -> SKIP (bdw-nuci7-2)
bdw-nuci7-2 total:226 pass:26 dwarn:0 dfail:1 fail:52 skip:147
bsw-nuc-2 total:225 pass:22 dwarn:0 dfail:1 fail:60 skip:142
byt-nuc total:225 pass:20 dwarn:0 dfail:1 fail:60 skip:144
hsw-brixbox total:226 pass:22 dwarn:0 dfail:1 fail:60 skip:143
hsw-gt2 total:226 pass:27 dwarn:0 dfail:1 fail:60 skip:138
skl-i7k-2 total:226 pass:22 dwarn:0 dfail:1 fail:60 skip:143
skl-nuci5 total:226 pass:26 dwarn:0 dfail:1 fail:60 skip:139
Results at /archive/results/CI_IGT_test/Patchwork_2141/
e6160ef8b9b3ddfcb1fd382716887e57a2896710 drm-intel-nightly: 2016y-05m-05d-08h-06m-20s UTC integration manifest
579b4fc drm/i915: Allow MI_LOAD_REGISTER_REG between whitelisted registers.
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