[Intel-gfx] [PATCH 09/13] drm/i915: Kill off dead code from skl_dpll0_enable()

[Jani Nikula]

On Wed, 11 May 2016, ville.syrjala at linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> We calculate the CDCLK_CTL value from scratch so no need to attempt
> some form of RMW first.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula at intel.com>


> ---
>  drivers/gpu/drm/i915/intel_display.c | 5 -----
>  1 file changed, 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 0186f775f353..a21f9d3fb869 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5566,17 +5566,12 @@ skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
>  	u32 val;
>  
>  	/* select the minimum CDCLK before enabling DPLL 0 */
> -	val = I915_READ(CDCLK_CTL);
> -	val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
> -	val |= CDCLK_FREQ_337_308;
> -
>  	if (required_vco == 8640)
>  		min_freq = 308570;
>  	else
>  		min_freq = 337500;
>  
>  	val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
> -
>  	I915_WRITE(CDCLK_CTL, val);
>  	POSTING_READ(CDCLK_CTL);

-- 
Jani Nikula, Intel Open Source Technology Center