[Intel-gfx] [PATCH 12/13] drm/i915: Program BXT_CDCLK_CD2X_PIPE

[Imre Deak]

On Wed, 2016-05-11 at 22:44 +0300, ville.syrjala at linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> BXT could change the CD2X divider synchronized with a single pipe.
> So assuming the DE PLL frequency doesn't need to be changed, we could
> change cdclk without shutting off the pipe (when only a single pipe is
> enabled). In the meantime let's configure CDCLK_CTL for non-double
> buffered CD2X update, although it shouldn't really matter as long as
> the selected pipe is disabled when reprogramming the divider.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

Reviewed-by: Imre Deak <imre.deak at intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h      | 5 +++--
>  drivers/gpu/drm/i915/intel_display.c | 5 +++++
>  2 files changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 54ce0b105956..27a781260d33 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7566,14 +7566,15 @@ enum skl_disp_power_wells {
>  #define  CDCLK_FREQ_540			(1<<26)
>  #define  CDCLK_FREQ_337_308		(2<<26)
>  #define  CDCLK_FREQ_675_617		(3<<26)
> -#define  CDCLK_FREQ_DECIMAL_MASK	(0x7ff)
> -
> +#define  BXT_CDCLK_CD2X_PIPE(pipe)	((pipe)<<20)
> +#define  BXT_CDCLK_CD2X_PIPE_NONE	BXT_CDCLK_CD2X_PIPE(3)
>  #define  BXT_CDCLK_CD2X_DIV_SEL_MASK	(3<<22)
>  #define  BXT_CDCLK_CD2X_DIV_SEL_1	(0<<22)
>  #define  BXT_CDCLK_CD2X_DIV_SEL_1_5	(1<<22)
>  #define  BXT_CDCLK_CD2X_DIV_SEL_2	(2<<22)
>  #define  BXT_CDCLK_CD2X_DIV_SEL_4	(3<<22)
>  #define  BXT_CDCLK_SSA_PRECHARGE_ENABLE	(1<<16)
> +#define  CDCLK_FREQ_DECIMAL_MASK	(0x7ff)
>  
>  /* LCPLL_CTL */
>  #define LCPLL1_CTL		_MMIO(0x46010)
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 61133fdedc8d..39990bfe47f2 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5434,6 +5434,11 @@ static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
>  			DRM_ERROR("timeout waiting for DE PLL lock\n");
>  
>  		val = I915_READ(CDCLK_CTL);
> +		/*
> +		 * FIXME if only the cd2x divider needs changing, it could be done
> +		 * without shutting off the pipe (if only one pipe is active).
> +		 */
> +		val |= BXT_CDCLK_CD2X_PIPE_NONE;
>  		val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
>  		val |= divider;
>  		/*