[Intel-gfx] [PATCH 5/6] drm/i915: Move CHV divider readout to intel_dpio_phy.c

[Ville Syrjälä]

On Fri, May 13, 2016 at 05:15:02PM +0300, Ander Conselvan de Oliveira wrote:
> Reading the dividers depends on sideband messaging, so it fits well if
> the other functions in intel_dpio_phy.c. The new function will also be
> used in a future patch.
> 
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h       |  2 ++
>  drivers/gpu/drm/i915/intel_display.c  | 18 +-----------------
>  drivers/gpu/drm/i915/intel_dpio_phy.c | 24 ++++++++++++++++++++++++
>  3 files changed, 27 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 7dfa555..149317c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3630,6 +3630,8 @@ void chv_phy_post_pll_disable(struct intel_encoder *encoder);
>  void chv_phy_prepare_pll(struct intel_crtc *crtc, u32 bestn,
>  			 u32 bestm1, u32 bestm2, u32 bestp1, u32 bestp2,
>  			 int vco);
> +void chv_phy_read_dividers(struct drm_i915_private *dev_priv,
> +			   enum pipe pipe, struct intel_dpll *clock);

_pll_dividers() again?

>  
>  void vlv_set_phy_signal_level(struct intel_encoder *encoder,
>  			      u32 demph_reg_value, u32 preemph_reg_value,
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 8d61263..5ba000a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -7892,30 +7892,14 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc,
>  	struct drm_device *dev = crtc->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	int pipe = pipe_config->cpu_transcoder;
> -	enum dpio_channel port = vlv_pipe_to_channel(pipe);
>  	struct intel_dpll clock;
> -	u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
>  	int refclk = 100000;
>  
>  	/* In case of DSI, DPLL will not be used */
>  	if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
>  		return;
>  
> -	mutex_lock(&dev_priv->sb_lock);
> -	cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
> -	pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
> -	pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
> -	pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
> -	pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
> -	mutex_unlock(&dev_priv->sb_lock);
> -
> -	clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
> -	clock.m2 = (pll_dw0 & 0xff) << 22;
> -	if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
> -		clock.m2 |= pll_dw2 & 0x3fffff;
> -	clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
> -	clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
> -	clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
> +	chv_phy_read_dividers(dev_priv, pipe, &clock);
>  
>  	pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
>  }
> diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
> index d28ef9f..2a5d333 100644
> --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> @@ -461,6 +461,30 @@ void chv_phy_prepare_pll(struct intel_crtc *crtc, u32 bestn,
>  	mutex_unlock(&dev_priv->sb_lock);
>  }
>  
> +void chv_phy_read_dividers(struct drm_i915_private *dev_priv,
> +			   enum pipe pipe, struct intel_dpll *clock)
> +{
> +	enum dpio_channel port = vlv_pipe_to_channel(pipe);
> +	u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
> +
> +	mutex_lock(&dev_priv->sb_lock);
> +	cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
> +	pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
> +	pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
> +	pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
> +	pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
> +	mutex_unlock(&dev_priv->sb_lock);
> +
> +	clock->m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
> +	clock->m2 = (pll_dw0 & 0xff) << 22;
> +	if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
> +		clock->m2 |= pll_dw2 & 0x3fffff;
> +	clock->n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
> +	clock->p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
> +	clock->p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
> +}
> +
> +
>  void vlv_set_phy_signal_level(struct intel_encoder *encoder,
>  			      u32 demph_reg_value, u32 preemph_reg_value,
>  			      u32 uniqtranscale_reg_value, u32 tx3_demph)
> -- 
> 2.5.5
> 
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-- 
Ville Syrjälä
Intel OTC