[Intel-gfx] ✗ Ro.CI.BAT: failure for drm/i915: SKL/KBL/BXT cdclk stuff

[Patchwork]

== Series Details ==

Series: drm/i915: SKL/KBL/BXT cdclk stuff
URL   : https://patchwork.freedesktop.org/series/7169/
State : failure

== Summary ==

Series 7169v1 drm/i915: SKL/KBL/BXT cdclk stuff
http://patchwork.freedesktop.org/api/1.0/series/7169/revisions/1/mbox

Test gem_exec_flush:
        Subgroup basic-batch-kernel-default-cmd:
                fail       -> PASS       (ro-byt-n2820)
Test kms_flip:
        Subgroup basic-flip-vs-wf_vblank:
                pass       -> FAIL       (ro-hsw-i3-4010u)
Test kms_pipe_crc_basic:
        Subgroup hang-read-crc-pipe-a:
                pass       -> DMESG-WARN (ro-ivb2-i7-3770)

ro-bdw-i5-5250u  total:219  pass:181  dwarn:0   dfail:0   fail:0   skip:38 
ro-bdw-i7-5557U  total:219  pass:206  dwarn:0   dfail:0   fail:0   skip:13 
ro-bdw-i7-5600u  total:219  pass:187  dwarn:0   dfail:0   fail:0   skip:32 
ro-bsw-n3050     total:219  pass:175  dwarn:0   dfail:0   fail:2   skip:42 
ro-byt-n2820     total:218  pass:175  dwarn:0   dfail:0   fail:2   skip:41 
ro-hsw-i3-4010u  total:218  pass:192  dwarn:0   dfail:0   fail:1   skip:25 
ro-hsw-i7-4770r  total:219  pass:194  dwarn:0   dfail:0   fail:0   skip:25 
ro-ilk-i7-620lm  total:219  pass:151  dwarn:0   dfail:0   fail:1   skip:67 
ro-ilk1-i5-650   total:214  pass:152  dwarn:0   dfail:0   fail:1   skip:61 
ro-ivb2-i7-3770  total:219  pass:186  dwarn:1   dfail:0   fail:0   skip:32 
ro-skl-i7-6700hq total:214  pass:190  dwarn:0   dfail:0   fail:0   skip:24 
ro-snb-i7-2620M  total:219  pass:177  dwarn:0   dfail:0   fail:1   skip:41 
ro-ivb-i7-3770 failed to connect after reboot

Results at /archive/results/CI_IGT_test/RO_Patchwork_900/

1a536db drm-intel-nightly: 2016y-05m-13d-21h-21m-06s UTC integration manifest
b974b6b drm/i915: Set BXT cdclk to minimum initially
c75fe510 drm/i915: Replace bxt_verify_cdclk_state() with a more generic cdclk check
ef3fb6c drm/i915: Make bxt_set_cdclk() operate in terms of the current vs target DE PLL vco
b8ee27d drm/i915: Rewrite broxton_get_display_clock_speed() in terms of the DE PLL vco/refclk
77095f2 drm/i915: Update cached cdclk state from broxton_init_cdclk()
7c27fe0 drm/i915: Store BXT DE PLL vco and ref clocks in dev_priv
351a2e3 drm/i915: Extract bxt DE PLL enable/disable from broxton_set_cdclk()
dabb9dd drm/i915: Store cdclk PLL reference clock under dev_priv
995467c drm/i915: Rename skl_vco_freq to cdclk_pll.vco
19f5564 drm/i915: Make 308 and 671 MHz cdclks more accurate on SKL
3499324 drm/i915: Move SKL+ DBUF enable/disable to display core init/uninit
75083d8 drm/i915: Unify SKL cdclk init paths
0b482fa drm/i915: Beef up skl_sanitize_cdclk() a bit
5fe223b drm/i915: Keep track of preferred cdclk vco frequency on SKL
b878f36 drm/i915: Allow enable/disable of DPLL0 around cdclk changes on SKL
8fbef2c drm/i915: Report the current DPLL0 vco on SKL/KBL
244d5cc drm/i915: Actually read out DPLL0 vco on skl from hardware
7d03efe drm/i915: Extract skl_calc_cdclk()
e2cd537 drm/i915: Move the SKL DPLL0 VCO computation into intel_dp_compute_config()
732fab3 drm/i915/skl: SKL CDCLK change on modeset tracking VCO
e53fa8e drm/i915: Fix BXT min_pixclk after state readout