[Intel-gfx] [PATCH 10/15] drm/i915: Generate addressing mode bit from flag in context.

[Tvrtko Ursulin]

On 15/05/16 18:32, Zhi Wang wrote:
> Previously the addressing mode bit in context descriptor is generated from
> context PPGTT. As we allow context could be used without PPGTT, and we
> still need to know the addressing mode during context submission, a flag
> is introduced.
>
> And the addressing mode bit will be generated from this flag.
>
> Signed-off-by: Zhi Wang <zhi.a.wang at intel.com>
> ---
>   drivers/gpu/drm/i915/i915_drv.h         | 1 +
>   drivers/gpu/drm/i915/i915_gem_context.c | 2 ++
>   drivers/gpu/drm/i915/intel_lrc.c        | 9 +++++----
>   3 files changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 4ac88b2..7f050a3 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -885,6 +885,7 @@ struct intel_context {
>   		bool skip_init_context;
>   		u32 ring_buffer_size;
>   	} engine[I915_NUM_ENGINES];
> +	bool use_48bit_addressing_mode;
>
>   	struct list_head link;
>   };
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index b952e37..b5b0849 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -343,6 +343,8 @@ i915_gem_create_context(struct drm_device *dev,
>   			ctx->ppgtt = ppgtt;
>   		} else
>   			ctx->ppgtt = dev_priv->mm.aliasing_ppgtt;
> +
> +		ctx->use_48bit_addressing_mode = USES_FULL_48BIT_PPGTT(dev);

Should be dev_priv, you added it in an earlier patch. Could replace the 
one usage of to_i915 in this function with it in that patch as well.

Regards,

Tvrtko

>   	}
>
>   	trace_i915_context_create(ctx);
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 3f04784..0a96d4a 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -214,7 +214,8 @@ enum {
>   	LEGACY_64B_CONTEXT
>   };
>   #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
> -#define GEN8_CTX_ADDRESSING_MODE(dev)  (USES_FULL_48BIT_PPGTT(dev) ?\
> +#define GEN8_CTX_ADDRESSING_MODE(ctx) \
> +		(ctx->use_48bit_addressing_mode ? \
>   		LEGACY_64B_CONTEXT :\
>   		LEGACY_32B_CONTEXT)
>   enum {
> @@ -281,8 +282,6 @@ logical_ring_init_platform_invariants(struct intel_engine_cs *engine)
>   					(engine->id == VCS || engine->id == VCS2);
>
>   	engine->ctx_desc_template = GEN8_CTX_VALID;
> -	engine->ctx_desc_template |= GEN8_CTX_ADDRESSING_MODE(dev_priv) <<
> -				   GEN8_CTX_ADDRESSING_MODE_SHIFT;
>   	if (IS_GEN8(dev_priv))
>   		engine->ctx_desc_template |= GEN8_CTX_L3LLC_COHERENT;
>   	engine->ctx_desc_template |= GEN8_CTX_PRIVILEGE;
> @@ -325,8 +324,10 @@ intel_lr_context_descriptor_update(struct intel_context *ctx,
>   	BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (1<<GEN8_CTX_ID_WIDTH));
>
>   	desc = engine->ctx_desc_template;			/* bits  0-11 */
> +	desc |= GEN8_CTX_ADDRESSING_MODE(ctx) <<		/* bits  3-4  */
> +		GEN8_CTX_ADDRESSING_MODE_SHIFT;
>   	desc |= ctx->engine[engine->id].lrc_vma->node.start +	/* bits 12-31 */
> -	       LRC_PPHWSP_PN * PAGE_SIZE;
> +		LRC_PPHWSP_PN * PAGE_SIZE;
>   	desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT;		/* bits 32-52 */
>
>   	ctx->engine[engine->id].lrc_desc = desc;
>