[Intel-gfx] [PATCH 01/21] drm/i915: Fix BXT min_pixclk after state readout

[Ville Syrjälä]

On Tue, May 17, 2016 at 09:09:15PM +0300, Imre Deak wrote:
> On Fri, 2016-05-13 at 23:41 +0300, ville.syrjala at linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > 
> > commit 4e5ca60fd35a ("drm/i915: Use ilk_max_pixel_rate() for BXT cdclk calculation")
> > tried to change BXT to use ilk_max_pixel_rate() to compute the
> > pipe pixel rate. I failed to notice that there was another place
> > in the state readout code that needs the same treatment. So let's
> > change that one too.
> > 
> > Should probably just change things to always compuyte the pipe pixel
> > rates, instead of just doing on platforms that can change cdclk
> > dynamically. But for now let's just move BXT fully over to the
> > side that uses ilk_pipe_pixel_rate().
> > 
> > Cc: Jani Nikula <jani.nikula at intel.com>
> > Fixes: 4e5ca60fd35a ("drm/i915: Use ilk_max_pixel_rate() for BXT cdclk calculation")
> > Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> Reviewed-by: Imre Deak <imre.deak at intel.com>
> 
> Btw, there is also skl_pipe_pixel_rate() that needs the same change.

Oh dear. Just how many of these things do we need? I'll send a patch to just
nuke the skl version.

> 
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 14 ++++++--------
> >  1 file changed, 6 insertions(+), 8 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index c5f0a6f30879..cc9a8b42fbc6 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -15748,18 +15748,16 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> >  		if (crtc_state->base.active) {
> >  			dev_priv->active_crtcs |= 1 << crtc->pipe;
> >  
> > -			if (IS_BROADWELL(dev_priv)) {
> > +			if (IS_BROXTON(dev_priv) || IS_BROADWELL(dev_priv))
> >  				pixclk = ilk_pipe_pixel_rate(crtc_state);
> > -
> > -				/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
> > -				if (crtc_state->ips_enabled)
> > -					pixclk = DIV_ROUND_UP(pixclk * 100, 95);
> > -			} else if (IS_VALLEYVIEW(dev_priv) ||
> > -				   IS_CHERRYVIEW(dev_priv) ||
> > -				   IS_BROXTON(dev_priv))
> > +			else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> >  				pixclk = crtc_state->base.adjusted_mode.crtc_clock;
> >  			else
> >  				WARN_ON(dev_priv->display.modeset_calc_cdclk);
> > +
> > +			/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
> > +			if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
> > +				pixclk = DIV_ROUND_UP(pixclk * 100, 95);
> >  		}
> >  
> >  		dev_priv->min_pixclk[crtc->pipe] = pixclk;

-- 
Ville Syrjälä
Intel OTC