[Intel-gfx] [PATCH 9/9] drm/i915: Introduce GVT context creation API

[Chris Wilson]

On Tue, May 17, 2016 at 04:19:09AM -0400, Zhi Wang wrote:
> GVT workload scheduler needs special host LRC contexts, the so called
> "shadow LRC context" to submit guest workload to host i915. During the
> guest workload submission, GVT fills the shadow LRC context with the
> content of guest LRC context: engine context is copied without changes,
> ring context is mostly owned by host i915.
> 
> The GVT-g workload scheduler flow:
> 
>          +-----------+                   +-----------+
>          | GVT Guest |                   | GVT Guest |
>          +-+-----^---+                   +-+-----^---+
>            |     |                         |     |
>            |     | GVT-g                   |     | GVT-g
> vELSP write|     | emulates     vELSP write|     | emulates
>            |     | Execlist/CSB            |     | Execlist/CSB
>            |     | Status                  |     | Status
>            |     |                         |     |
>     +------v-----+-------------------------v-----+---------+
>     |           GVT Virtual Execlist Submission            |
>     +------+-------------------------------+---------------+
>            |                               |
>            | Per-VM/Ring Workoad Q         | Per-VM/Ring Workload Q
>    +---------------------+--+      +------------------------+
>        +---v--------+    ^             +---v--------+
>        |GVT Workload|... |             |GVT Workload|...
>        +------------+    |             +------------+
>                          |
>                          | Pick Workload from Q
>     +--------------------+---------------------------------+
>     |                GVT Workload Scheduler                |
>     +--------------------+---------------------------------+
>                          |         * Shadow guest LRC context
>                   +------v------+  * Shadow guest ring buffer
>                   | GVT Context |  * Scan/Patch guest RB instructions
>                   +------+------+
>                          |
>                          v
>               Host i915 GEM Submission
> v5:
> - Only compile this feature when CONFIG_DRM_I915_GVT is enabled.
> - Rebase the code into new repo.
> - Add a comment about the ring buffer size.
> 
> v2:
> 
> Mostly based on Daniel's idea. Call the refactored core logic of GEM
> context creation service and LRC context creation service to create the GVT
> context.
> 
> Signed-off-by: Zhi Wang <zhi.a.wang at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h         |  1 +
>  drivers/gpu/drm/i915/i915_gem_context.c | 31 +++++++++++++++++++++++++++++++
>  2 files changed, 32 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b8f1e9a..7e5a506 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3398,6 +3398,7 @@ i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
>  void i915_gem_context_free(struct kref *ctx_ref);
>  struct drm_i915_gem_object *
>  i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
> +struct intel_context *i915_gem_create_gvt_context(struct drm_device *dev);
>  static inline void i915_gem_context_reference(struct intel_context *ctx)
>  {
>  	kref_get(&ctx->ref);
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index 057e2fe..a69bb86 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -354,6 +354,37 @@ err_destroy:
>  	return ERR_PTR(ret);
>  }
>  
> +#if IS_ENABLED(CONFIG_DRM_I915_GVT)
> +/**
> + * i915_gem_create_gvt_context - create a GVT GEM context
> + * @dev: drm device *
> + *
> + * This function is used to create a GVT specific GEM context.
> + *
> + * Returns:
> + * pointer to intel_context on success, NULL if failed
> + *
> + */
> +struct intel_context *
> +i915_gem_create_gvt_context(struct drm_device *dev)

i915_gem_context_create_gvt
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre