[Intel-gfx] [PATCH 00/21] drm/i915: SKL/KBL/BXT cdclk stuff

[Ville Syrjälä]

On Fri, May 13, 2016 at 11:41:19PM +0300, ville.syrjala at linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> Here's my second installment of SKL+ cdclk stuff. I've picked up Clint's latest
> SKL/KBL cdclk patch and expanded on it quite a bit. After this series we're
> capable of actually changing the DPLL0 VCO frequency dynamically, and a lot of
> the code gets a much more uniform feel to it between SKL/KBL vs. BXT. This
> should make it possible to land some future hardware work on top as well,
> without making the code an awful mess.
> 
> Series available here:
> git://github.com/vsyrjala/linux.git skl_bxt_cdclk_part_2
> 
> Clint Taylor (1):
>   drm/i915/skl: SKL CDCLK change on modeset tracking VCO
> 
> Ville Syrjälä (20):
>   drm/i915: Fix BXT min_pixclk after state readout
>   drm/i915: Move the SKL DPLL0 VCO computation into
>     intel_dp_compute_config()
>   drm/i915: Extract skl_calc_cdclk()
>   drm/i915: Actually read out DPLL0 vco on skl from hardware
>   drm/i915: Report the current DPLL0 vco on SKL/KBL
>   drm/i915: Allow enable/disable of DPLL0 around cdclk changes on SKL
>   drm/i915: Keep track of preferred cdclk vco frequency on SKL
>   drm/i915: Beef up skl_sanitize_cdclk() a bit
>   drm/i915: Unify SKL cdclk init paths
>   drm/i915: Move SKL+ DBUF enable/disable to display core init/uninit
>   drm/i915: Make 308 and 671 MHz cdclks more accurate on SKL
>   drm/i915: Rename skl_vco_freq to cdclk_pll.vco
>   drm/i915: Store cdclk PLL reference clock under dev_priv
>   drm/i915: Extract bxt DE PLL enable/disable from broxton_set_cdclk()
>   drm/i915: Store BXT DE PLL vco and ref clocks in dev_priv
>   drm/i915: Update cached cdclk state from broxton_init_cdclk()
>   drm/i915: Rewrite broxton_get_display_clock_speed() in terms of the DE
>     PLL vco/refclk
>   drm/i915: Make bxt_set_cdclk() operate in terms of the current vs
>     target DE PLL vco
>   drm/i915: Replace bxt_verify_cdclk_state() with a more generic cdclk
>     check
>   drm/i915: Set BXT cdclk to minimum initially

Entire series pushed to dinq. Thanks for the reviews.

> 
>  drivers/gpu/drm/i915/i915_drv.h         |   6 +-
>  drivers/gpu/drm/i915/intel_display.c    | 623 +++++++++++++++++++-------------
>  drivers/gpu/drm/i915/intel_dp.c         |  21 ++
>  drivers/gpu/drm/i915/intel_dpll_mgr.c   |  19 +-
>  drivers/gpu/drm/i915/intel_drv.h        |   7 +-
>  drivers/gpu/drm/i915/intel_runtime_pm.c |  45 ++-
>  6 files changed, 443 insertions(+), 278 deletions(-)
> 
> -- 
> 2.7.4

-- 
Ville Syrjälä
Intel OTC