[Intel-gfx] [PATCH v2 1/1] drm/i915: Update GEN6_PMINTRMSK setup with GuC enabled

[Chris Wilson]

On Mon, May 30, 2016 at 04:51:03PM +0530, Sagar Arun Kamble wrote:
> @@ -4580,6 +4590,8 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>  	else
>  		dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
>  
> +	dev_priv->rps.pm_intr_mask = ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;

I was hoping for something along the lines of

	dev_priv->rps.pm_intr_keep = 0;
	if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
		dev_priv->rps.pm_intr_keep |= GEN6_PM_RP_UP_EI_EXPIRED;

	if (INTEL_INFO(dev_priv)->gen >= 8) {
		u32 tmp;

		dev_priv->rps.pm_intr_keep |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;

		/*
		 * If PM interrupts are routed to GuC, Set mask for ARAT Expired
		 * interrupt based on mask set by GuC.
		 */
		tmp = I915_READ(GEN6_PMINTRMSK));
		if (tmp & GEN8_PMINTR_REDIRECT_TO_NON_DISP)
			dev_priv->rps.pm_intr_keep = tmp | ~GEN8_ARAT_EXPIRED_INT_MASK;
	}

then gen6_sanitize_rps_pm_mask() just becomes
	mask &= ~dev_priv->rps.pm_intr_keep

Note that reading PMINTRMSK to answer a question of whether we have
enabled something is odd, i.e. shouldn't we be applying the
dev_priv->rps.pm_intr_keep fixup when we redirect interrupts to the GuC?

> @@ -4715,7 +4717,20 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
>  		else
>  			gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
>  		dev_priv->rps.last_adj = 0;
> -		I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
> +
> +		/*
> +		 * If PM interrupts are routed to GuC, Set mask for ARAT Expired
> +		 * interrupt based on mask set by GuC.
> +		*/
> +		if (INTEL_INFO(dev_priv)->gen >= 8) {
> +			if (dev_priv->rps.pm_intr_mask &
> +			    GEN8_PMINTR_REDIRECT_TO_NON_DISP)
> +				mask &= dev_priv->rps.pm_intr_mask |
> +					~GEN8_ARAT_EXPIRED_INT_MASK;
> +			else
> +				mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;
> +		}
> +		I915_WRITE(GEN6_PMINTRMSK, mask);

This should be a call to gen6_sanitize_rps_pm_mask(). Ville has a patch
on the list to do that, please pull it in.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre