[Intel-gfx] [PATCH] drm/i915/bxt: Don't set OCL2_LDOFUSE_PWR_DIS bit in phy init sequence

[Imre Deak]

On ti, 2016-11-01 at 13:11 +0200, Ander Conselvan de Oliveira wrote:
> Hardware engineers confirmed that writing to it has no effect, as implied by
> the FIXME comment.
> 
> Cc: Imre Deak <imre.deak at intel.com>
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira at intel.com>

You could also remove the corresponding comment
from bxt_ddi_phy_verify_state(), either way:

Reviewed-by: Imre Deak <imre.deak at intel.com>

> ---
>  drivers/gpu/drm/i915/intel_dpio_phy.c | 16 ----------------
>  1 file changed, 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
> index 4a6164a..e95b291 100644
> --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> @@ -365,22 +365,6 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
>  		I915_WRITE(BXT_PORT_CL2CM_DW6(phy), val);
>  	}
>  
> -	val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
> -	val &= ~OCL2_LDOFUSE_PWR_DIS;
> -	/*
> -	 * On PHY1 disable power on the second channel, since no port is
> -	 * connected there. On PHY0 both channels have a port, so leave it
> -	 * enabled.
> -	 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
> -	 * power down the second channel on PHY0 as well.
> -	 *
> -	 * FIXME: Clarify programming of the following, the register is
> -	 * read-only with bit 6 fixed at 0 at least in stepping A.
> -	 */
> -	if (!phy_info->dual_channel)
> -		val |= OCL2_LDOFUSE_PWR_DIS;
> -	I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
> -
>  	if (phy_info->rcomp_phy != -1) {
>  		uint32_t grc_code;
>  		/*