[Intel-gfx] [PATCH 1/3] drm/i915: Remove chipset flush after cache flush

[Chris Wilson]

On Mon, Nov 07, 2016 at 02:01:46PM +0200, Joonas Lahtinen wrote:
> On su, 2016-11-06 at 12:59 +0000, Chris Wilson wrote:
> > We always flush the chipset prior to executing with the GPU, so we can
> > skip the flush during ordinary domain management.
> > 
> > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> 
> Maybe even add?
> 
> Fixes: dcd79934b0dd ("drm/i915: Unconditionally flush any chipset buffers before execbuf")

It is just an optimisation - I don't want to imply that we should be
pushing this to stable trees as it should not be fixing user visible
bugs. Slightly worried about the GTT access paths, they have never been
as coherent as claimed, so I worry...
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre