[Intel-gfx] [PATCH v2 06/11] drm/i915/scheduler: Record all dependencies upon request construction
Tvrtko Ursulin
tvrtko.ursulin at linux.intel.com
Thu Nov 10 14:45:39 UTC 2016
On 07/11/2016 13:59, Chris Wilson wrote:
> The scheduler needs to know the dependencies of each request for the
> lifetime of the request, as it may choose to reschedule the requests at
> any time and must ensure the dependency tree is not broken. This is in
> additional to using the fence to only allow execution after all
> dependencies have been completed.
>
> One option was to extend the fence to support the bidirectional
> dependency tracking required by the scheduler. However the mismatch in
> lifetimes between the submit fence and the request essentially meant
> that we had to build a completely separate struct (and we could not
> simply reuse the existing waitqueue in the fence for one half of the
> dependency tracking). The extra dependency tracking simply did not mesh
> well with the fence, and keeping it separate both keeps the fence
> implementation simpler and allows us to extend the dependency tracking
> into a priority tree (whilst maintaining support for reordering the
> tree).
>
> To avoid the additional allocations and list manipulations, the use of
> the priotree is disabled when there are no schedulers to use it.
>
> v2: Create a dedicated slab for i915_dependency.
> Rename the lists.
>
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 7 +-
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_gem.c | 14 ++-
> drivers/gpu/drm/i915/i915_gem_request.c | 96 +++++++++++++++++++-
> drivers/gpu/drm/i915/i915_gem_request.h | 40 ++++++++-
> drivers/gpu/drm/i915/i915_guc_submission.c | 1 +
> drivers/gpu/drm/i915/intel_engine_cs.c | 3 +-
> drivers/gpu/drm/i915/intel_lrc.c | 135 +++++++++++++++++++++++++++--
> drivers/gpu/drm/i915/intel_ringbuffer.h | 3 +-
> 9 files changed, 282 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 3cb96d260dfb..dac435680e98 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -631,8 +631,9 @@ static void print_request(struct seq_file *m,
> struct drm_i915_gem_request *rq,
> const char *prefix)
> {
> - seq_printf(m, "%s%x [%x:%x] @ %d: %s\n", prefix,
> + seq_printf(m, "%s%x [%x:%x] prio=%d @ %dms: %s\n", prefix,
> rq->global_seqno, rq->ctx->hw_id, rq->fence.seqno,
> + rq->priotree.priority,
> jiffies_to_msecs(jiffies - rq->emitted_jiffies),
> rq->timeline->common->name);
> }
> @@ -3218,6 +3219,7 @@ static int i915_engine_info(struct seq_file *m, void *unused)
>
> if (i915.enable_execlists) {
> u32 ptr, read, write;
> + struct rb_node *rb;
>
> seq_printf(m, "\tExeclist status: 0x%08x %08x\n",
> I915_READ(RING_EXECLIST_STATUS_LO(engine)),
> @@ -3257,7 +3259,8 @@ static int i915_engine_info(struct seq_file *m, void *unused)
> rcu_read_unlock();
>
> spin_lock_irq(&engine->timeline->lock);
> - list_for_each_entry(rq, &engine->execlist_queue, execlist_link) {
> + for (rb = engine->execlist_first; rb; rb = rb_next(rb)) {
> + rq = rb_entry(rb, typeof(*rq), priotree.node);
> print_request(m, rq, "\t\tQ ");
> }
> spin_unlock_irq(&engine->timeline->lock);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 4735b4177100..e790147209f3 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1791,6 +1791,7 @@ struct drm_i915_private {
> struct kmem_cache *objects;
> struct kmem_cache *vmas;
> struct kmem_cache *requests;
> + struct kmem_cache *dependencies;
>
> const struct intel_device_info info;
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index df803e82eb07..a4dc2da2323a 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -2693,10 +2693,11 @@ static void i915_gem_cleanup_engine(struct intel_engine_cs *engine)
>
> spin_lock_irqsave(&engine->timeline->lock, flags);
>
> - INIT_LIST_HEAD(&engine->execlist_queue);
> i915_gem_request_put(engine->execlist_port[0].request);
> i915_gem_request_put(engine->execlist_port[1].request);
> memset(engine->execlist_port, 0, sizeof(engine->execlist_port));
> + engine->execlist_queue = RB_ROOT;
> + engine->execlist_first = NULL;
>
> spin_unlock_irqrestore(&engine->timeline->lock, flags);
> }
> @@ -4754,12 +4755,18 @@ i915_gem_load_init(struct drm_device *dev)
> if (!dev_priv->requests)
> goto err_vmas;
>
> + dev_priv->dependencies = KMEM_CACHE(i915_dependency,
> + SLAB_HWCACHE_ALIGN |
> + SLAB_RECLAIM_ACCOUNT);
> + if (!dev_priv->dependencies)
> + goto err_requests;
> +
> mutex_lock(&dev_priv->drm.struct_mutex);
> INIT_LIST_HEAD(&dev_priv->gt.timelines);
> err = i915_gem_timeline_init__global(dev_priv);
> mutex_unlock(&dev_priv->drm.struct_mutex);
> if (err)
> - goto err_requests;
> + goto err_dependencies;
>
> INIT_LIST_HEAD(&dev_priv->context_list);
> INIT_WORK(&dev_priv->mm.free_work, __i915_gem_free_work);
> @@ -4787,6 +4794,8 @@ i915_gem_load_init(struct drm_device *dev)
>
> return 0;
>
> +err_dependencies:
> + kmem_cache_destroy(dev_priv->dependencies);
> err_requests:
> kmem_cache_destroy(dev_priv->requests);
> err_vmas:
> @@ -4803,6 +4812,7 @@ void i915_gem_load_cleanup(struct drm_device *dev)
>
> WARN_ON(!llist_empty(&dev_priv->mm.free_list));
>
> + kmem_cache_destroy(dev_priv->dependencies);
> kmem_cache_destroy(dev_priv->requests);
> kmem_cache_destroy(dev_priv->vmas);
> kmem_cache_destroy(dev_priv->objects);
> diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c
> index 93f77df9bc51..278b103a4e95 100644
> --- a/drivers/gpu/drm/i915/i915_gem_request.c
> +++ b/drivers/gpu/drm/i915/i915_gem_request.c
> @@ -113,6 +113,82 @@ i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
> spin_unlock(&file_priv->mm.lock);
> }
>
> +static struct i915_dependency *
> +i915_dependency_alloc(struct drm_i915_private *i915)
> +{
> + return kmem_cache_alloc(i915->dependencies, GFP_KERNEL);
> +}
> +
> +static void
> +i915_dependency_free(struct drm_i915_private *i915,
> + struct i915_dependency *dep)
> +{
> + kmem_cache_free(i915->dependencies, dep);
> +}
> +
> +static void
> +__i915_priotree_add_dependency(struct i915_priotree *pt,
> + struct i915_priotree *signal,
> + struct i915_dependency *dep,
> + unsigned long flags)
> +{
> + INIT_LIST_HEAD(&dep->dfs_link);
> + list_add(&dep->wait_link, &signal->waiters_list);
> + list_add(&dep->signal_link, &pt->signalers_list);
> + dep->signaler = signal;
> + dep->flags = flags;
> +}
> +
> +static int
> +i915_priotree_add_dependency(struct drm_i915_private *i915,
> + struct i915_priotree *pt,
> + struct i915_priotree *signal)
> +{
> + struct i915_dependency *dep;
> +
> + dep = i915_dependency_alloc(i915);
> + if (!dep)
> + return -ENOMEM;
> +
> + __i915_priotree_add_dependency(pt, signal, dep, I915_DEPENDENCY_ALLOC);
> + return 0;
> +}
> +
> +static void
> +i915_priotree_fini(struct drm_i915_private *i915, struct i915_priotree *pt)
> +{
> + struct i915_dependency *dep, *next;
> +
> + GEM_BUG_ON(!RB_EMPTY_NODE(&pt->node));
> +
> + /* Everyone we depended upon (the fences we wait to be signaled)
> + * should retire before us and remove themselves from our list.
> + * However, retirement is run independently on each timeline and
> + * so we may be called out-of-order.
> + */
> + list_for_each_entry_safe(dep, next, &pt->signalers_list, signal_link) {
> + list_del(&dep->wait_link);
> + if (dep->flags & I915_DEPENDENCY_ALLOC)
> + i915_dependency_free(i915, dep);
> + }
> +
> + /* Remove ourselves from everyone who depends upon us */
> + list_for_each_entry_safe(dep, next, &pt->waiters_list, wait_link) {
> + list_del(&dep->signal_link);
> + if (dep->flags & I915_DEPENDENCY_ALLOC)
> + i915_dependency_free(i915, dep);
> + }
> +}
> +
> +static void
> +i915_priotree_init(struct i915_priotree *pt)
> +{
> + INIT_LIST_HEAD(&pt->signalers_list);
> + INIT_LIST_HEAD(&pt->waiters_list);
> + RB_CLEAR_NODE(&pt->node);
> + pt->priority = INT_MIN;
Not I915_PRIORITY_MIN? Or it has to be smaller? In which case
BUILD_BUG_ON(INT_MIN >= I915_PRIORITY_MIN)?
> +}
> +
> void i915_gem_retire_noop(struct i915_gem_active *active,
> struct drm_i915_gem_request *request)
> {
> @@ -182,6 +258,8 @@ static void i915_gem_request_retire(struct drm_i915_gem_request *request)
> i915_gem_context_put(request->ctx);
>
> dma_fence_signal(&request->fence);
> +
> + i915_priotree_fini(request->i915, &request->priotree);
> i915_gem_request_put(request);
> }
>
> @@ -461,6 +539,8 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
> */
> i915_sw_fence_await_sw_fence(&req->execute, &req->submit, &req->execq);
>
> + i915_priotree_init(&req->priotree);
> +
> INIT_LIST_HEAD(&req->active_list);
> req->i915 = dev_priv;
> req->engine = engine;
> @@ -514,6 +594,14 @@ i915_gem_request_await_request(struct drm_i915_gem_request *to,
>
> GEM_BUG_ON(to == from);
>
> + if (to->engine->schedule) {
> + ret = i915_priotree_add_dependency(to->i915,
> + &to->priotree,
> + &from->priotree);
> + if (ret < 0)
> + return ret;
> + }
> +
> if (to->timeline == from->timeline)
> return 0;
>
> @@ -737,9 +825,15 @@ void __i915_add_request(struct drm_i915_gem_request *request, bool flush_caches)
>
> prev = i915_gem_active_raw(&timeline->last_request,
> &request->i915->drm.struct_mutex);
> - if (prev)
> + if (prev) {
> i915_sw_fence_await_sw_fence(&request->submit, &prev->submit,
> &request->submitq);
> + if (engine->schedule)
> + __i915_priotree_add_dependency(&request->priotree,
> + &prev->priotree,
> + &request->dep,
> + 0);
> + }
>
> spin_lock_irq(&timeline->lock);
> list_add_tail(&request->link, &timeline->requests);
> diff --git a/drivers/gpu/drm/i915/i915_gem_request.h b/drivers/gpu/drm/i915/i915_gem_request.h
> index d8904863d3d9..584d76170df3 100644
> --- a/drivers/gpu/drm/i915/i915_gem_request.h
> +++ b/drivers/gpu/drm/i915/i915_gem_request.h
> @@ -41,6 +41,32 @@ struct intel_signal_node {
> struct intel_wait wait;
> };
>
> +struct i915_dependency {
> + struct i915_priotree *signaler;
> + struct list_head signal_link;
> + struct list_head wait_link;
> + struct list_head dfs_link;
> + unsigned long flags;
> +#define I915_DEPENDENCY_ALLOC BIT(0)
> +};
> +
> +/* Requests exist in a complex web of interdependencies. Each request
> + * has to wait for some other request to complete before it is ready to be run
> + * (e.g. we have to wait until the pixels have been rendering into a texture
> + * before we can copy from it). We track the readiness of a request in terms
> + * of fences, but we also need to keep the dependency tree for the lifetime
> + * of the request (beyond the life of an individual fence). We use the tree
> + * at various points to reorder the requests whilst keeping the requests
> + * in order with respect to their various dependencies.
> + */
> +struct i915_priotree {
> + struct list_head signalers_list; /* those before us, we depend upon */
> + struct list_head waiters_list; /* those after us, they depend upon us */
> + struct rb_node node;
> + int priority;
> +#define I915_PRIORITY_MAX 1024
> +};
> +
> /**
> * Request queue structure.
> *
> @@ -102,6 +128,17 @@ struct drm_i915_gem_request {
> wait_queue_t submitq;
> wait_queue_t execq;
>
> + /* A list of everyone we wait upon, and everyone who waits upon us.
> + * Even though we will not be submitted to the hardware before the
> + * submit fence is signaled (it waits for all external events as well
> + * as our own requests), the scheduler still needs to know the
> + * dependency tree for the lifetime of the request (from execbuf
> + * to retirement), i.e. bidirectional dependency information for the
> + * request not tied to individual fences.
> + */
> + struct i915_priotree priotree;
> + struct i915_dependency dep;
> +
> u32 global_seqno;
>
> /** GEM sequence number associated with the previous request,
> @@ -158,9 +195,6 @@ struct drm_i915_gem_request {
> struct drm_i915_file_private *file_priv;
> /** file_priv list entry for this request */
> struct list_head client_list;
> -
> - /** Link in the execlist submission queue, guarded by execlist_lock. */
> - struct list_head execlist_link;
> };
>
> extern const struct dma_fence_ops i915_fence_ops;
> diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
> index 83438c6a8864..7c6819968307 100644
> --- a/drivers/gpu/drm/i915/i915_guc_submission.c
> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
> @@ -1532,6 +1532,7 @@ int i915_guc_submission_enable(struct drm_i915_private *dev_priv)
> /* Take over from manual control of ELSP (execlists) */
> for_each_engine(engine, dev_priv, id) {
> engine->submit_request = i915_guc_submit;
> + engine->schedule = NULL;
>
> /* Replay the current set of previously submitted requests */
> list_for_each_entry(request,
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index c9171a058478..3da4d466e332 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -239,7 +239,8 @@ static void intel_engine_init_timeline(struct intel_engine_cs *engine)
> */
> void intel_engine_setup_common(struct intel_engine_cs *engine)
> {
> - INIT_LIST_HEAD(&engine->execlist_queue);
> + engine->execlist_queue = RB_ROOT;
> + engine->execlist_first = NULL;
>
> intel_engine_init_timeline(engine);
> intel_engine_init_hangcheck(engine);
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 94933f4297bb..af944a246511 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -432,9 +432,10 @@ static bool can_merge_ctx(const struct i915_gem_context *prev,
>
> static void execlists_dequeue(struct intel_engine_cs *engine)
> {
> - struct drm_i915_gem_request *cursor, *last;
> + struct drm_i915_gem_request *last;
> struct execlist_port *port = engine->execlist_port;
> unsigned long flags;
> + struct rb_node *rb;
> bool submit = false;
>
> last = port->request;
> @@ -471,7 +472,11 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
> */
>
> spin_lock_irqsave(&engine->timeline->lock, flags);
> - list_for_each_entry(cursor, &engine->execlist_queue, execlist_link) {
> + rb = engine->execlist_first;
> + while (rb) {
> + struct drm_i915_gem_request *cursor =
> + rb_entry(rb, typeof(*cursor), priotree.node);
> +
> /* Can we combine this request with the current port? It has to
> * be the same context/ringbuffer and not have any exceptions
> * (e.g. GVT saying never to combine contexts).
> @@ -503,6 +508,11 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
> port++;
> }
>
> + rb = rb_next(rb);
> + rb_erase(&cursor->priotree.node, &engine->execlist_queue);
> + RB_CLEAR_NODE(&cursor->priotree.node);
> + cursor->priotree.priority = INT_MAX;
What does setting the priority to INT_MAX here do?
> +
> /* We keep the previous context alive until we retire the
> * following request. This ensures that any the context object
> * is still pinned for any residual writes the HW makes into it
> @@ -517,11 +527,8 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
> submit = true;
> }
> if (submit) {
> - /* Decouple all the requests submitted from the queue */
> - engine->execlist_queue.next = &cursor->execlist_link;
> - cursor->execlist_link.prev = &engine->execlist_queue;
> -
> i915_gem_request_assign(&port->request, last);
> + engine->execlist_first = rb;
> }
> spin_unlock_irqrestore(&engine->timeline->lock, flags);
>
> @@ -604,17 +611,126 @@ static void intel_lrc_irq_handler(unsigned long data)
> intel_uncore_forcewake_put(dev_priv, engine->fw_domains);
> }
>
> +static bool insert_request(struct i915_priotree *pt, struct rb_root *root)
> +{
> + struct rb_node **p, *rb;
> + bool first = true;
> +
> + /* most positive priority is scheduled first, equal priorities fifo */
> + rb = NULL;
> + p = &root->rb_node;
> + while (*p) {
> + struct i915_priotree *pos;
> +
> + rb = *p;
> + pos = rb_entry(rb, typeof(*pos), node);
> + if (pt->priority > pos->priority) {
> + p = &rb->rb_left;
> + } else {
> + p = &rb->rb_right;
> + first = false;
> + }
> + }
> + rb_link_node(&pt->node, rb, p);
> + rb_insert_color(&pt->node, root);
> +
> + return first;
> +}
> +
> static void execlists_submit_request(struct drm_i915_gem_request *request)
> {
> struct intel_engine_cs *engine = request->engine;
>
> assert_spin_locked(&engine->timeline->lock);
>
> - list_add_tail(&request->execlist_link, &engine->execlist_queue);
> + if (insert_request(&request->priotree, &engine->execlist_queue))
> + engine->execlist_first = &request->priotree.node;
> if (execlists_elsp_idle(engine))
> tasklet_hi_schedule(&engine->irq_tasklet);
> }
>
> +static struct intel_engine_cs *
> +pt_lock_engine(struct i915_priotree *pt, struct intel_engine_cs *locked)
> +{
> + struct intel_engine_cs *engine;
> +
> + engine = container_of(pt,
> + struct drm_i915_gem_request,
> + priotree)->engine;
> + if (engine != locked) {
> + if (locked)
> + spin_unlock_irq(&locked->timeline->lock);
> + spin_lock_irq(&engine->timeline->lock);
> + }
> +
> + return engine;
> +}
Ha, cute. :)
> +
> +static void execlists_schedule(struct drm_i915_gem_request *request, int prio)
> +{
> + struct intel_engine_cs *engine = NULL;
> + struct i915_dependency *dep, *p;
> + struct i915_dependency stack;
> + LIST_HEAD(dfs);
> +
> + if (prio <= READ_ONCE(request->priotree.priority))
> + return;
> +
> + /* Need BKL in order to use the temporary link inside i915_dependency */
> + lockdep_assert_held(&request->i915->drm.struct_mutex);
Could use a new i915 submission lock, but I suppose this is OK to start
with.
> +
> + stack.signaler = &request->priotree;
> + list_add(&stack.dfs_link, &dfs);
> +
Tada, onto the DFS which I am not familiar with - but there's always
Wikipedia. :)
> + /* Recursively bump all dependent priorities to match the new request */
> + list_for_each_entry_safe(dep, p, &dfs, dfs_link) {
> + struct i915_priotree *pt = dep->signaler;
> +
> + list_for_each_entry(p, &pt->signalers_list, signal_link)
> + if (prio > READ_ONCE(p->signaler->priority))
> + list_move_tail(&p->dfs_link, &dfs);
> +
> + p = list_first_entry(&dep->dfs_link, typeof(*p), dfs_link);
This was fun. :)
> + if (!RB_EMPTY_NODE(&pt->node))
> + continue;
> +
> + engine = pt_lock_engine(pt, engine);
> +
> + /* If it is not already in the rbtree, we can update the
> + * priority inplace and skip over it (and its dependencies)
> + * if it is referenced again as we descend the dfs.
> + */
Are you sure it is OK to ignore the dependencies for new requests? I
don't see why it would be.
> + if (prio > pt->priority && RB_EMPTY_NODE(&pt->node)) {
Isn't the node guaranteed to be empty from the earlier test and continue?
> + pt->priority = prio;
> + list_del_init(&dep->dfs_link);
> + }
> + }
> +
> + /* Fifo and depth-first replacement ensure our deps execute before us */
> + list_for_each_entry_safe_reverse(dep, p, &dfs, dfs_link) {
> + struct i915_priotree *pt = dep->signaler;
> +
> + INIT_LIST_HEAD(&dep->dfs_link);
> +
> + engine = pt_lock_engine(pt, engine);
> +
> + if (prio <= pt->priority)
> + continue;
How would these priorities end up in the list? The first loop skips over
them.
> +
> + GEM_BUG_ON(RB_EMPTY_NODE(&pt->node));
> +
> + pt->priority = prio;
> + rb_erase(&pt->node, &engine->execlist_queue);
> + if (insert_request(pt, &engine->execlist_queue))
> + engine->execlist_first = &pt->node;
> + }
> +
> + if (engine)
> + spin_unlock_irq(&engine->timeline->lock);
> +
> + /* XXX Do we need to preempt to make room for us and our deps? */
> +}
> +
> int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request)
> {
> struct intel_engine_cs *engine = request->engine;
> @@ -1651,8 +1767,10 @@ void intel_execlists_enable_submission(struct drm_i915_private *dev_priv)
> struct intel_engine_cs *engine;
> enum intel_engine_id id;
>
> - for_each_engine(engine, dev_priv, id)
> + for_each_engine(engine, dev_priv, id) {
> engine->submit_request = execlists_submit_request;
> + engine->schedule = execlists_schedule;
> + }
> }
>
> static void
> @@ -1665,6 +1783,7 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
> engine->emit_breadcrumb = gen8_emit_breadcrumb;
> engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_sz;
> engine->submit_request = execlists_submit_request;
> + engine->schedule = execlists_schedule;
>
> engine->irq_enable = gen8_logical_ring_enable_irq;
> engine->irq_disable = gen8_logical_ring_disable_irq;
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 75991a3c694b..cbc148863a03 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -348,7 +348,8 @@ struct intel_engine_cs {
> struct drm_i915_gem_request *request;
> unsigned int count;
> } execlist_port[2];
> - struct list_head execlist_queue;
> + struct rb_root execlist_queue;
> + struct rb_node *execlist_first;
> unsigned int fw_domains;
> bool disable_lite_restore_wa;
> bool preempt_wa;
>
Regards,
Tvrtko
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