[Intel-gfx] ✓ Fi.CI.BAT: success for Geminilake enabling (rev2)

[Patchwork]

== Series Details ==

Series: Geminilake enabling (rev2)
URL   : https://patchwork.freedesktop.org/series/15118/
State : success

== Summary ==

Series 15118v2 Geminilake enabling
https://patchwork.freedesktop.org/api/1.0/series/15118/revisions/2/mbox/


fi-bdw-5557u     total:244  pass:229  dwarn:0   dfail:0   fail:0   skip:15 
fi-bsw-n3050     total:244  pass:204  dwarn:0   dfail:0   fail:0   skip:40 
fi-bxt-t5700     total:244  pass:216  dwarn:0   dfail:0   fail:0   skip:28 
fi-byt-j1900     total:244  pass:216  dwarn:0   dfail:0   fail:0   skip:28 
fi-byt-n2820     total:244  pass:212  dwarn:0   dfail:0   fail:0   skip:32 
fi-hsw-4770      total:244  pass:224  dwarn:0   dfail:0   fail:0   skip:20 
fi-hsw-4770r     total:244  pass:224  dwarn:0   dfail:0   fail:0   skip:20 
fi-ilk-650       total:244  pass:191  dwarn:0   dfail:0   fail:0   skip:53 
fi-ivb-3520m     total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-ivb-3770      total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-kbl-7200u     total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-skl-6260u     total:244  pass:230  dwarn:0   dfail:0   fail:0   skip:14 
fi-skl-6700hq    total:244  pass:223  dwarn:0   dfail:0   fail:0   skip:21 
fi-skl-6700k     total:244  pass:222  dwarn:1   dfail:0   fail:0   skip:21 
fi-skl-6770hq    total:244  pass:230  dwarn:0   dfail:0   fail:0   skip:14 
fi-snb-2520m     total:244  pass:212  dwarn:0   dfail:0   fail:0   skip:32 
fi-snb-2600      total:244  pass:211  dwarn:0   dfail:0   fail:0   skip:33 

7b290828029bfbbb50b1b907b197adc3f30e0d22 drm-intel-nightly: 2016y-11m-11d-13h-18m-42s UTC integration manifest
5e4b76b drm/i915/glk: Configure number of sprite planes properly
ff6061e drm/i915/glk: Implement core display init/uninit sequence for geminilake
ab20ac43 drm/i915/glk: Allow dotclock up to 2 * cdclk on geminilake
3b702ad drm/i915/glk: Reuse broxton's cdclk code for GLK
2845b00 drm/i915/glk: Update Port PLL enable sequence for Geminilkae
a723276 drm/i915/glk: Set DCC delay range 2 in PLL enable sequence
d970945 drm/i915/glk: Implement Geminilake DDI init sequence
f7e6b49 drm/i915/glk: Add power wells for Geminilake
0ad651c1 drm/i915/glk: Set DDI PHY lane lane optimization for Geminilake too
f415efb drm/i915/glk: Force DDI initialization.
78881dd drm/i915/glk: Reuse broxton code for geminilake
171b4ba drm/i915/glk: Add a IS_GEN9_LP() macro
4c69daa drm/i915/glk: Add Geminilake PCI IDs
55ff300 drm/i915/glk: Introduce Geminilake platform definition
668846a drm/i915: Create a common GEN9_LP_FEATURE.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_2969/