[Intel-gfx] [PATCH v3] drm/i915: fix the dequeue logic for single_port_submission context

[He, Min]

> -----Original Message-----
> From: Chris Wilson [mailto:chris at chris-wilson.co.uk]
> Sent: Thursday, November 17, 2016 4:01 PM
> To: He, Min <min.he at intel.com>
> Cc: intel-gfx at lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH v3] drm/i915: fix the dequeue logic for
> single_port_submission context
> 
> On Wed, Nov 16, 2016 at 10:05:04PM +0800, Min He wrote:
> > For a singl_port_submission context, it can only be submitted to port 0,
> > and there shouldn't be any other context in port 1 at the same time. This
> > is required by GVT-g context to have an opportunity to save/restore some
> > non-hw context render registers.
> 
> This statement is not true. It has the opportunity to modify the GVT
> context if a non-GVT context was in port 0 or port 1.
If a non-GVT context is in port 0, and a GVT context in port 1, after non-GVT
context completes, GPU will switch to GVT context directly, and we will lose
the opportunity to save the non-GVT context registers and restore GVT context
registers. So non-GVT context's register will impact GVT context. 
And vice versa. 

> 
> > This patch is to implement the correct logic in execlists_dequeue.
> 
> I object. This is not the correct logic here, but to workaround a
> failure in GVT.
> 
> Any way pushed until GVT is fixed.
> -Chris
> 
> --
> Chris Wilson, Intel Open Source Technology Centre