[Intel-gfx] [PATCH v2 13/15] drm/i915: dev_priv cleanup in intel_display.c
Maarten Lankhorst
maarten.lankhorst at linux.intel.com
Thu Nov 17 14:20:34 UTC 2016
Op 16-11-16 om 13:32 schreef Tvrtko Ursulin:
> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
>
> v2: Rebase.
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 3 +-
> drivers/gpu/drm/i915/intel_display.c | 167 +++++++++++++++--------------------
> 3 files changed, 75 insertions(+), 97 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index ce34e7ab44ab..445fec9c2841 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -495,7 +495,7 @@ static unsigned int i915_vga_set_decode(void *cookie, bool state)
> {
> struct drm_device *dev = cookie;
>
> - intel_modeset_vga_set_state(dev, state);
> + intel_modeset_vga_set_state(to_i915(dev), state);
dev_priv = cookie, and fixup vga_client_register to pass dev_priv instead of dev?
either way
Reviewed-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com>
> if (state)
> return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
> VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 69e3658f00e2..70a736a02e26 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3481,7 +3481,8 @@ extern void intel_modeset_gem_init(struct drm_device *dev);
> extern void intel_modeset_cleanup(struct drm_device *dev);
> extern int intel_connector_register(struct drm_connector *);
> extern void intel_connector_unregister(struct drm_connector *);
> -extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
> +extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
> + bool state);
> extern void intel_display_resume(struct drm_device *dev);
> extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
> extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index da1e29ec9eb6..e4f1985a5592 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1035,9 +1035,8 @@ enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
> return crtc->config->cpu_transcoder;
> }
>
> -static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
> +static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe)
> {
> - struct drm_i915_private *dev_priv = to_i915(dev);
> i915_reg_t reg = PIPEDSL(pipe);
> u32 line1, line2;
> u32 line_mask;
> @@ -1072,12 +1071,11 @@ static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
> */
> static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
> {
> - struct drm_device *dev = crtc->base.dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
> enum pipe pipe = crtc->pipe;
>
> - if (INTEL_INFO(dev)->gen >= 4) {
> + if (INTEL_GEN(dev_priv) >= 4) {
> i915_reg_t reg = PIPECONF(cpu_transcoder);
>
> /* Wait for the Pipe State to go off */
> @@ -1087,7 +1085,7 @@ static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
> WARN(1, "pipe_off wait timed out\n");
> } else {
> /* Wait for the display line to settle */
> - if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
> + if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
> WARN(1, "pipe_off wait timed out\n");
> }
> }
> @@ -1293,11 +1291,10 @@ static void assert_plane(struct drm_i915_private *dev_priv,
> static void assert_planes_disabled(struct drm_i915_private *dev_priv,
> enum pipe pipe)
> {
> - struct drm_device *dev = &dev_priv->drm;
> int i;
>
> /* Primary planes are fixed to pipes on gen4+ */
> - if (INTEL_INFO(dev)->gen >= 4) {
> + if (INTEL_GEN(dev_priv) >= 4) {
> u32 val = I915_READ(DSPCNTR(pipe));
> I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
> "plane %c assertion failure, should be disabled but not\n",
> @@ -1319,10 +1316,9 @@ static void assert_planes_disabled(struct drm_i915_private *dev_priv,
> static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
> enum pipe pipe)
> {
> - struct drm_device *dev = &dev_priv->drm;
> int sprite;
>
> - if (INTEL_INFO(dev)->gen >= 9) {
> + if (INTEL_GEN(dev_priv) >= 9) {
> for_each_sprite(dev_priv, pipe, sprite) {
> u32 val = I915_READ(PLANE_CTL(pipe, sprite));
> I915_STATE_WARN(val & PLANE_CTL_ENABLE,
> @@ -1336,12 +1332,12 @@ static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
> "sprite %c assertion failure, should be off on pipe %c but is still active\n",
> sprite_name(pipe, sprite), pipe_name(pipe));
> }
> - } else if (INTEL_INFO(dev)->gen >= 7) {
> + } else if (INTEL_GEN(dev_priv) >= 7) {
> u32 val = I915_READ(SPRCTL(pipe));
> I915_STATE_WARN(val & SPRITE_ENABLE,
> "sprite %c assertion failure, should be off on pipe %c but is still active\n",
> plane_name(pipe), pipe_name(pipe));
> - } else if (INTEL_INFO(dev)->gen >= 5) {
> + } else if (INTEL_GEN(dev_priv) >= 5) {
> u32 val = I915_READ(DVSCNTR(pipe));
> I915_STATE_WARN(val & DVS_ENABLE,
> "sprite %c assertion failure, should be off on pipe %c but is still active\n",
> @@ -1595,12 +1591,12 @@ static void chv_enable_pll(struct intel_crtc *crtc,
> }
> }
>
> -static int intel_num_dvo_pipes(struct drm_device *dev)
> +static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
> {
> struct intel_crtc *crtc;
> int count = 0;
>
> - for_each_intel_crtc(dev, crtc) {
> + for_each_intel_crtc(&dev_priv->drm, crtc) {
> count += crtc->base.state->active &&
> intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
> }
> @@ -1610,8 +1606,7 @@ static int intel_num_dvo_pipes(struct drm_device *dev)
>
> static void i9xx_enable_pll(struct intel_crtc *crtc)
> {
> - struct drm_device *dev = crtc->base.dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> i915_reg_t reg = DPLL(crtc->pipe);
> u32 dpll = crtc->config->dpll_hw_state.dpll;
>
> @@ -1622,7 +1617,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
> assert_panel_unlocked(dev_priv, crtc->pipe);
>
> /* Enable DVO 2x clock on both PLLs if necessary */
> - if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev) > 0) {
> + if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
> /*
> * It appears to be important that we don't enable this
> * for the current pipe before otherwise configuring the
> @@ -1647,7 +1642,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
> POSTING_READ(reg);
> udelay(150);
>
> - if (INTEL_INFO(dev)->gen >= 4) {
> + if (INTEL_GEN(dev_priv) >= 4) {
> I915_WRITE(DPLL_MD(crtc->pipe),
> crtc->config->dpll_hw_state.dpll_md);
> } else {
> @@ -1682,14 +1677,13 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
> */
> static void i9xx_disable_pll(struct intel_crtc *crtc)
> {
> - struct drm_device *dev = crtc->base.dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
>
> /* Disable DVO 2x clock on both PLLs if necessary */
> if (IS_I830(dev_priv) &&
> intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
> - !intel_num_dvo_pipes(dev)) {
> + !intel_num_dvo_pipes(dev_priv)) {
> I915_WRITE(DPLL(PIPE_B),
> I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
> I915_WRITE(DPLL(PIPE_A),
> @@ -3004,8 +2998,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
> const struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state)
> {
> - struct drm_device *dev = primary->dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct drm_i915_private *dev_priv = to_i915(primary->dev);
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
> struct drm_framebuffer *fb = plane_state->base.fb;
> int plane = intel_crtc->plane;
> @@ -3020,7 +3013,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
>
> dspcntr |= DISPLAY_PLANE_ENABLE;
>
> - if (INTEL_INFO(dev)->gen < 4) {
> + if (INTEL_GEN(dev_priv) < 4) {
> if (intel_crtc->pipe == PIPE_B)
> dspcntr |= DISPPLANE_SEL_PIPE_B;
>
> @@ -3080,7 +3073,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
>
> intel_add_fb_offsets(&x, &y, plane_state, 0);
>
> - if (INTEL_INFO(dev)->gen >= 4)
> + if (INTEL_GEN(dev_priv) >= 4)
> intel_crtc->dspaddr_offset =
> intel_compute_tile_offset(&x, &y, plane_state, 0);
>
> @@ -3093,7 +3086,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
>
> linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
>
> - if (INTEL_INFO(dev)->gen < 4)
> + if (INTEL_GEN(dev_priv) < 4)
> intel_crtc->dspaddr_offset = linear_offset;
>
> intel_crtc->adjusted_x = x;
> @@ -3102,7 +3095,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
> I915_WRITE(reg, dspcntr);
>
> I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
> - if (INTEL_INFO(dev)->gen >= 4) {
> + if (INTEL_GEN(dev_priv) >= 4) {
> I915_WRITE(DSPSURF(plane),
> intel_fb_gtt_offset(fb, rotation) +
> intel_crtc->dspaddr_offset);
> @@ -3680,8 +3673,7 @@ static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
> static void intel_update_pipe_config(struct intel_crtc *crtc,
> struct intel_crtc_state *old_crtc_state)
> {
> - struct drm_device *dev = crtc->base.dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_crtc_state *pipe_config =
> to_intel_crtc_state(crtc->base.state);
>
> @@ -3706,7 +3698,7 @@ static void intel_update_pipe_config(struct intel_crtc *crtc,
> (pipe_config->pipe_src_h - 1));
>
> /* on skylake this is done by detaching scalers */
> - if (INTEL_INFO(dev)->gen >= 9) {
> + if (INTEL_GEN(dev_priv) >= 9) {
> skl_detach_scalers(crtc);
>
> if (pipe_config->pch_pfit.enabled)
> @@ -5406,8 +5398,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> struct drm_atomic_state *old_state)
> {
> struct drm_crtc *crtc = pipe_config->base.crtc;
> - struct drm_device *dev = crtc->dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> int pipe = intel_crtc->pipe, hsw_workaround_pipe;
> enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
> @@ -5467,7 +5458,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> if (!transcoder_is_dsi(cpu_transcoder))
> intel_ddi_enable_pipe_clock(intel_crtc);
>
> - if (INTEL_INFO(dev)->gen >= 9)
> + if (INTEL_GEN(dev_priv) >= 9)
> skylake_pfit_enable(intel_crtc);
> else
> ironlake_pfit_enable(intel_crtc);
> @@ -5600,8 +5591,7 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
> struct drm_atomic_state *old_state)
> {
> struct drm_crtc *crtc = old_crtc_state->base.crtc;
> - struct drm_device *dev = crtc->dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
>
> @@ -5624,7 +5614,7 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
> if (!transcoder_is_dsi(cpu_transcoder))
> intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
>
> - if (INTEL_INFO(dev)->gen >= 9)
> + if (INTEL_GEN(dev_priv) >= 9)
> skylake_scaler_disable(intel_crtc);
> else
> ironlake_pfit_disable(intel_crtc, false);
> @@ -7193,7 +7183,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
> const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> int clock_limit = dev_priv->max_dotclk_freq;
>
> - if (INTEL_INFO(dev)->gen < 4) {
> + if (INTEL_GEN(dev_priv) < 4) {
> clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
>
> /*
> @@ -7787,12 +7777,11 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
> struct intel_link_m_n *m_n,
> struct intel_link_m_n *m2_n2)
> {
> - struct drm_device *dev = crtc->base.dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> int pipe = crtc->pipe;
> enum transcoder transcoder = crtc->config->cpu_transcoder;
>
> - if (INTEL_INFO(dev)->gen >= 5) {
> + if (INTEL_GEN(dev_priv) >= 5) {
> I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
> I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
> I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
> @@ -8246,8 +8235,7 @@ static void i8xx_compute_dpll(struct intel_crtc *crtc,
>
> static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
> {
> - struct drm_device *dev = intel_crtc->base.dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
> enum pipe pipe = intel_crtc->pipe;
> enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
> const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
> @@ -8273,7 +8261,7 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
> vsyncshift += adjusted_mode->crtc_htotal;
> }
>
> - if (INTEL_INFO(dev)->gen > 3)
> + if (INTEL_GEN(dev_priv) > 3)
> I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
>
> I915_WRITE(HTOTAL(cpu_transcoder),
> @@ -8396,8 +8384,7 @@ void intel_mode_from_pipe_config(struct drm_display_mode *mode,
>
> static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
> {
> - struct drm_device *dev = intel_crtc->base.dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
> uint32_t pipeconf;
>
> pipeconf = 0;
> @@ -8443,7 +8430,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
> }
>
> if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
> - if (INTEL_INFO(dev)->gen < 4 ||
> + if (INTEL_GEN(dev_priv) < 4 ||
> intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
> pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
> else
> @@ -8651,8 +8638,7 @@ static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
> static void i9xx_get_pfit_config(struct intel_crtc *crtc,
> struct intel_crtc_state *pipe_config)
> {
> - struct drm_device *dev = crtc->base.dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> uint32_t tmp;
>
> if (INTEL_GEN(dev_priv) <= 3 &&
> @@ -8664,7 +8650,7 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc,
> return;
>
> /* Check whether the pfit is attached to our pipe. */
> - if (INTEL_INFO(dev)->gen < 4) {
> + if (INTEL_GEN(dev_priv) < 4) {
> if (crtc->pipe != PIPE_B)
> return;
> } else {
> @@ -8728,7 +8714,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
>
> fb = &intel_fb->base;
>
> - if (INTEL_INFO(dev)->gen >= 4) {
> + if (INTEL_GEN(dev_priv) >= 4) {
> if (val & DISPPLANE_TILED) {
> plane_config->tiling = I915_TILING_X;
> fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
> @@ -8740,7 +8726,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
> fb->pixel_format = fourcc;
> fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
>
> - if (INTEL_INFO(dev)->gen >= 4) {
> + if (INTEL_GEN(dev_priv) >= 4) {
> if (plane_config->tiling)
> offset = I915_READ(DSPTILEOFF(plane));
> else
> @@ -8809,8 +8795,7 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc,
> static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
> struct intel_crtc_state *pipe_config)
> {
> - struct drm_device *dev = crtc->base.dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum intel_display_power_domain power_domain;
> uint32_t tmp;
> bool ret;
> @@ -8849,7 +8834,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
> (tmp & PIPECONF_COLOR_RANGE_SELECT))
> pipe_config->limited_color_range = true;
>
> - if (INTEL_INFO(dev)->gen < 4)
> + if (INTEL_GEN(dev_priv) < 4)
> pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
>
> intel_get_pipe_timings(crtc, pipe_config);
> @@ -8857,7 +8842,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
>
> i9xx_get_pfit_config(crtc, pipe_config);
>
> - if (INTEL_INFO(dev)->gen >= 4) {
> + if (INTEL_GEN(dev_priv) >= 4) {
> /* No way to read it out on pipes B and C */
> if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
> tmp = dev_priv->chv_dpll_md[crtc->pipe];
> @@ -9654,11 +9639,10 @@ static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
> struct intel_link_m_n *m_n,
> struct intel_link_m_n *m2_n2)
> {
> - struct drm_device *dev = crtc->base.dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
>
> - if (INTEL_INFO(dev)->gen >= 5) {
> + if (INTEL_GEN(dev_priv) >= 5) {
> m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
> m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
> m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
> @@ -9670,7 +9654,7 @@ static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
> * gen < 8) and if DRRS is supported (to make sure the
> * registers are not unnecessarily read).
> */
> - if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
> + if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
> crtc->config->has_drrs) {
> m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
> m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
> @@ -9872,7 +9856,7 @@ ironlake_get_initial_plane_config(struct intel_crtc *crtc,
>
> fb = &intel_fb->base;
>
> - if (INTEL_INFO(dev)->gen >= 4) {
> + if (INTEL_GEN(dev_priv) >= 4) {
> if (val & DISPPLANE_TILED) {
> plane_config->tiling = I915_TILING_X;
> fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
> @@ -10662,8 +10646,7 @@ static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
> static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
> struct intel_crtc_state *pipe_config)
> {
> - struct drm_device *dev = crtc->base.dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_shared_dpll *pll;
> enum port port;
> uint32_t tmp;
> @@ -10690,7 +10673,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
> * DDI E. So just check whether this pipe is wired to DDI E and whether
> * the PCH transcoder is on.
> */
> - if (INTEL_INFO(dev)->gen < 9 &&
> + if (INTEL_GEN(dev_priv) < 9 &&
> (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
> pipe_config->has_pch_encoder = true;
>
> @@ -10705,8 +10688,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
> static bool haswell_get_pipe_config(struct intel_crtc *crtc,
> struct intel_crtc_state *pipe_config)
> {
> - struct drm_device *dev = crtc->base.dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum intel_display_power_domain power_domain;
> unsigned long power_domain_mask;
> bool active;
> @@ -10739,7 +10721,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
> pipe_config->gamma_mode =
> I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
>
> - if (INTEL_INFO(dev)->gen >= 9) {
> + if (INTEL_GEN(dev_priv) >= 9) {
> skl_init_scalers(dev_priv, crtc, pipe_config);
>
> pipe_config->scaler_state.scaler_id = -1;
> @@ -10749,7 +10731,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
> power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
> if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
> power_domain_mask |= BIT(power_domain);
> - if (INTEL_INFO(dev)->gen >= 9)
> + if (INTEL_GEN(dev_priv) >= 9)
> skylake_get_pfit_config(crtc, pipe_config);
> else
> ironlake_get_pfit_config(crtc, pipe_config);
> @@ -12181,7 +12163,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
> * TILEOFF/LINOFF registers can't be changed via MI display flips.
> * Note that pitch changes could also affect these register.
> */
> - if (INTEL_INFO(dev)->gen > 3 &&
> + if (INTEL_GEN(dev_priv) > 3 &&
> (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
> fb->pitches[0] != crtc->primary->fb->pitches[0]))
> return -EINVAL;
> @@ -12256,7 +12238,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
> engine = NULL;
> } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
> engine = dev_priv->engine[BCS];
> - } else if (INTEL_INFO(dev)->gen >= 7) {
> + } else if (INTEL_GEN(dev_priv) >= 7) {
> engine = i915_gem_object_last_write_engine(obj);
> if (engine == NULL || engine->id != RCS)
> engine = dev_priv->engine[BCS];
> @@ -12513,7 +12495,7 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
>
> /* Pre-gen9 platforms need two-step watermark updates */
> if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
> - INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
> + INTEL_GEN(dev_priv) < 9 && dev_priv->display.optimize_watermarks)
> to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
>
> if (visible || was_visible)
> @@ -12618,7 +12600,7 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
> * old state and the new state. We can program these
> * immediately.
> */
> - ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
> + ret = dev_priv->display.compute_intermediate_wm(dev,
> intel_crtc,
> pipe_config);
> if (ret) {
> @@ -12630,7 +12612,7 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
> pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
> }
>
> - if (INTEL_INFO(dev)->gen >= 9) {
> + if (INTEL_GEN(dev_priv) >= 9) {
> if (mode_changed)
> ret = skl_update_scaler_crtc(pipe_config);
>
> @@ -13187,12 +13169,11 @@ intel_compare_link_m_n(const struct intel_link_m_n *m_n,
> }
>
> static bool
> -intel_pipe_config_compare(struct drm_device *dev,
> +intel_pipe_config_compare(struct drm_i915_private *dev_priv,
> struct intel_crtc_state *current_config,
> struct intel_crtc_state *pipe_config,
> bool adjust)
> {
> - struct drm_i915_private *dev_priv = to_i915(dev);
> bool ret = true;
>
> #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
> @@ -13312,7 +13293,7 @@ intel_pipe_config_compare(struct drm_device *dev,
> PIPE_CONF_CHECK_I(lane_count);
> PIPE_CONF_CHECK_X(lane_lat_optim_mask);
>
> - if (INTEL_INFO(dev)->gen < 8) {
> + if (INTEL_GEN(dev_priv) < 8) {
> PIPE_CONF_CHECK_M_N(dp_m_n);
>
> if (current_config->has_drrs)
> @@ -13361,7 +13342,7 @@ intel_pipe_config_compare(struct drm_device *dev,
>
> PIPE_CONF_CHECK_X(gmch_pfit.control);
> /* pfit ratios are autocomputed by the hw on gen4+ */
> - if (INTEL_INFO(dev)->gen < 4)
> + if (INTEL_GEN(dev_priv) < 4)
> PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
> PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
>
> @@ -13436,8 +13417,7 @@ static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
> static void verify_wm_state(struct drm_crtc *crtc,
> struct drm_crtc_state *new_state)
> {
> - struct drm_device *dev = crtc->dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> struct skl_ddb_allocation hw_ddb, *sw_ddb;
> struct skl_pipe_wm hw_wm, *sw_wm;
> struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
> @@ -13446,7 +13426,7 @@ static void verify_wm_state(struct drm_crtc *crtc,
> const enum pipe pipe = intel_crtc->pipe;
> int plane, level, max_level = ilk_wm_max_level(dev_priv);
>
> - if (INTEL_INFO(dev)->gen < 9 || !new_state->active)
> + if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
> return;
>
> skl_pipe_wm_get_hw_state(crtc, &hw_wm);
> @@ -13675,7 +13655,7 @@ verify_crtc_state(struct drm_crtc *crtc,
> intel_pipe_config_sanity_check(dev_priv, pipe_config);
>
> sw_config = to_intel_crtc_state(crtc->state);
> - if (!intel_pipe_config_compare(dev, sw_config,
> + if (!intel_pipe_config_compare(dev_priv, sw_config,
> pipe_config, false)) {
> I915_STATE_WARN(1, "pipe state doesn't match!\n");
> intel_dump_pipe_config(intel_crtc, pipe_config,
> @@ -14095,7 +14075,7 @@ static int intel_atomic_check(struct drm_device *dev,
> }
>
> if (i915.fastboot &&
> - intel_pipe_config_compare(dev,
> + intel_pipe_config_compare(dev_priv,
> to_intel_crtc_state(crtc->state),
> pipe_config, true)) {
> crtc_state->mode_changed = false;
> @@ -15425,11 +15405,9 @@ static bool has_edp_a(struct drm_i915_private *dev_priv)
> return true;
> }
>
> -static bool intel_crt_present(struct drm_device *dev)
> +static bool intel_crt_present(struct drm_i915_private *dev_priv)
> {
> - struct drm_i915_private *dev_priv = to_i915(dev);
> -
> - if (INTEL_INFO(dev)->gen >= 9)
> + if (INTEL_GEN(dev_priv) >= 9)
> return false;
>
> if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
> @@ -15503,7 +15481,7 @@ static void intel_setup_outputs(struct drm_device *dev)
> */
> intel_lvds_init(dev);
>
> - if (intel_crt_present(dev))
> + if (intel_crt_present(dev_priv))
> intel_crt_init(dev);
>
> if (IS_BROXTON(dev_priv)) {
> @@ -15793,7 +15771,7 @@ static int intel_framebuffer_init(struct drm_device *dev,
> switch (mode_cmd->modifier[0]) {
> case I915_FORMAT_MOD_Y_TILED:
> case I915_FORMAT_MOD_Yf_TILED:
> - if (INTEL_INFO(dev)->gen < 9) {
> + if (INTEL_GEN(dev_priv) < 9) {
> DRM_DEBUG("Unsupported tiling 0x%llx!\n",
> mode_cmd->modifier[0]);
> return -EINVAL;
> @@ -15856,7 +15834,7 @@ static int intel_framebuffer_init(struct drm_device *dev,
> case DRM_FORMAT_ARGB8888:
> break;
> case DRM_FORMAT_XRGB1555:
> - if (INTEL_INFO(dev)->gen > 3) {
> + if (INTEL_GEN(dev_priv) > 3) {
> DRM_DEBUG("unsupported pixel format: %s\n",
> drm_get_format_name(mode_cmd->pixel_format, &format_name));
> return -EINVAL;
> @@ -15864,7 +15842,7 @@ static int intel_framebuffer_init(struct drm_device *dev,
> break;
> case DRM_FORMAT_ABGR8888:
> if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
> - INTEL_INFO(dev)->gen < 9) {
> + INTEL_GEN(dev_priv) < 9) {
> DRM_DEBUG("unsupported pixel format: %s\n",
> drm_get_format_name(mode_cmd->pixel_format, &format_name));
> return -EINVAL;
> @@ -15873,7 +15851,7 @@ static int intel_framebuffer_init(struct drm_device *dev,
> case DRM_FORMAT_XBGR8888:
> case DRM_FORMAT_XRGB2101010:
> case DRM_FORMAT_XBGR2101010:
> - if (INTEL_INFO(dev)->gen < 4) {
> + if (INTEL_GEN(dev_priv) < 4) {
> DRM_DEBUG("unsupported pixel format: %s\n",
> drm_get_format_name(mode_cmd->pixel_format, &format_name));
> return -EINVAL;
> @@ -15890,7 +15868,7 @@ static int intel_framebuffer_init(struct drm_device *dev,
> case DRM_FORMAT_UYVY:
> case DRM_FORMAT_YVYU:
> case DRM_FORMAT_VYUY:
> - if (INTEL_INFO(dev)->gen < 5) {
> + if (INTEL_GEN(dev_priv) < 5) {
> DRM_DEBUG("unsupported pixel format: %s\n",
> drm_get_format_name(mode_cmd->pixel_format, &format_name));
> return -EINVAL;
> @@ -16667,7 +16645,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
> /* We need to sanitize the plane -> pipe mapping first because this will
> * disable the crtc (and hence change the state) if it is wrong. Note
> * that gen4+ has a fixed plane -> pipe mapping. */
> - if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
> + if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {
> bool plane;
>
> DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
> @@ -17177,10 +17155,9 @@ void intel_connector_attach_encoder(struct intel_connector *connector,
> /*
> * set vga decode state - true == enable VGA decode
> */
> -int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
> +int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
> {
> - struct drm_i915_private *dev_priv = to_i915(dev);
> - unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
> + unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
> u16 gmch_ctrl;
>
> if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
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