[Intel-gfx] [PATCH] drm/i915/bxt: Use smaller 8/3X MIPI clock divider value for dual link.

[Bob Paauwe]

For a single link (channel) DSI panel we want to use a larger divider
and keep the clock rate down to save power when in DPI/video mode. However
when using a dual-link DSI panel this may reduce the clock below what's
needed to get a stable display.

Use the smaller divider (faster clock) for either DBI/command mode or
when using dual link.

Signed-off-by: Bob Paauwe <bob.j.paauwe at intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_pll.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 56eff60..9edc57e 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -414,8 +414,13 @@ static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port,
 	rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2;
 	rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2;
 
-	/* As per bpsec program the 8/3X clock divider to the below value */
-	if (dev_priv->vbt.dsi.config->is_cmd_mode)
+	/*
+	 * Set the 8/3X clock to divide by 3 for DBI mode as it needs a
+	 * faster clock than DPI mode. However, dual link panels also
+	 * need the faster clock, even when in DPI mode.
+	 */
+	if (dev_priv->vbt.dsi.config->is_cmd_mode ||
+	    dev_priv->vbt.dsi.config->dual_link)
 		mipi_8by3_divider = 0x2;
 	else
 		mipi_8by3_divider = 0x3;
-- 
2.7.4