[Intel-gfx] [PATCH v5 3/8] drm/i915/kbl: IPC workaround for kabylake

[Paulo Zanoni]

Em Sex, 2016-11-18 às 20:39 +0530, Mahesh Kumar escreveu:
> IPC (Isoch Priority Control) may cause underflows.
> 
> KBL WA: When IPC is enabled, watermark latency values must be
> increased
> by 4us across all levels. This brings level 0 up to 6us.
> 
> Signed-off-by: Mahesh Kumar <mahesh1.kumar at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index 7090a7c..df39b50 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3599,6 +3599,10 @@ static int skl_compute_plane_wm(const struct
> drm_i915_private *dev_priv,
>  		return 0;
>  	}
>  
> +	/* IPC WA for kabylake */
> +	if (IS_KABYLAKE(dev_priv) && dev_priv->ipc_enabled)
> +		latency += 4;
> +

Nitpick: put this a little below so it's next to the other code that
changes the latency.

With or without this:
Reviewed-by: Paulo Zanoni <paulo.r.zanoni at intel.com>

>  	y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED ||
>  				fb->modifier ==
> I915_FORMAT_MOD_Yf_TILED;
>  	x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;