[Intel-gfx] [PATCH] drm/i915: Move the release of PT page to the upper caller

[Zhenyu Wang]

On 2016.11.22 14:38:19 +0000, Chris Wilson wrote:
> On Tue, Nov 22, 2016 at 09:29:40PM +0800, Zhi Wang wrote:
> > Hi guys:
> >     Would you mind to have a quick review on this patch? :P The
> > linux guest under GVT-g couldn't boot up without this patch in the
> > newer kernel.
> > 
> > Thanks,
> > Zhi.
> > 
> > On 11/21/16 19:44, Zhi Wang wrote:
> > >a PT page will be released if it doesn't contain any meaningful mappings
> > >during PPGTT page table shrinking. The PT entry in the upper level will
> > >be set to a scratch entry.
> > >
> > >Normally this works nicely, but in virtualization world, the PPGTT page
> > >table is tracked by hypervisor. Releasing the PT page before modifying
> > >the upper level PT entry would cause extra efforts.
> > >
> > >As the tracked page has been returned to OS before losing track from
> > >hypervisor, it could be written in any pattern. Hypervisor has to recognize
> > >if a page is still being used as a PT page by validating these writing
> > >patterns. It's complicated. Better let the guest modify the PT entry in
> > >upper level PT first, then release the PT page.
> > >
> > >Cc: Michał Winiarski <michal.winiarski at intel.com>
> > >Cc: Michel Thierry <michel.thierry at intel.com>
> > >Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
> > >Cc: Chris Wilson <chris at chris-wilson.co.uk>
> > >Cc: Zhenyu Wang <zhenyuw at linux.intel.com>
> > >Cc: Zhiyuan Lv <zhiyuan.lv at intel.com>
> > >Signed-off-by: Zhi Wang <zhi.a.wang at intel.com>
> 
> The original didn't make it to me, so I just assumed a list issue.
> 
> For the record, I'd like to have some more detail on just when the hv is
> doing the page scanning. It makes it sound like you are actively
> scanning an idle range.
> 
> Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>

Note that this should be queued for 4.9 fix otherwise 4.9 will be broken
as guest kernel version for GVT-g.

Thanks

-- 
Open Source Technology Center, Intel ltd.

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