[Intel-gfx] [PATCH v2] drm/i915/guc: Drop guc2host/host2guc from names

Chris Wilson chris at chris-wilson.co.uk
Fri Nov 25 13:03:11 UTC 2016


On Fri, Nov 25, 2016 at 01:29:21PM +0100, Arkadiusz Hiler wrote:
> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
> index 324ea90..9ccb8f8 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> @@ -489,18 +489,18 @@ union guc_log_control {
>  } __packed;
>  
>  /* This Action will be programmed in C180 - SOFT_SCRATCH_O_REG */
> -enum host2guc_action {
> -	HOST2GUC_ACTION_DEFAULT = 0x0,
> -	HOST2GUC_ACTION_SAMPLE_FORCEWAKE = 0x6,
> -	HOST2GUC_ACTION_ALLOCATE_DOORBELL = 0x10,
> -	HOST2GUC_ACTION_DEALLOCATE_DOORBELL = 0x20,
> -	HOST2GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE = 0x30,
> -	HOST2GUC_ACTION_FORCE_LOG_BUFFER_FLUSH = 0x302,
> -	HOST2GUC_ACTION_ENTER_S_STATE = 0x501,
> -	HOST2GUC_ACTION_EXIT_S_STATE = 0x502,
> -	HOST2GUC_ACTION_SLPC_REQUEST = 0x3003,
> -	HOST2GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
> -	HOST2GUC_ACTION_LIMIT
> +enum intel_guc_send_action {
> +	INTEL_GUC_ACTION_DEFAULT = 0x0,
> +	INTEL_GUC_ACTION_SAMPLE_FORCEWAKE = 0x6,
> +	INTEL_GUC_ACTION_ALLOCATE_DOORBELL = 0x10,
> +	INTEL_GUC_ACTION_DEALLOCATE_DOORBELL = 0x20,
> +	INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE = 0x30,
> +	INTEL_GUC_ACTION_FORCE_LOG_BUFFER_FLUSH = 0x302,
> +	INTEL_GUC_ACTION_ENTER_S_STATE = 0x501,
> +	INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
> +	INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
> +	INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
> +	INTEL_GUC_ACTION_LIMIT
>  };
>  
>  /*
> @@ -509,22 +509,25 @@ enum host2guc_action {
>   * by the fact that all the MASK bits are set. The remaining bits
>   * give more detail.
>   */
> -#define	GUC2HOST_RESPONSE_MASK		((u32)0xF0000000)
> -#define	GUC2HOST_IS_RESPONSE(x) 	((u32)(x) >= GUC2HOST_RESPONSE_MASK)
> -#define	GUC2HOST_STATUS(x)		(GUC2HOST_RESPONSE_MASK | (x))
> +#define	INTEL_GUC_RECV_MASK	((u32)0xF0000000)
> +#define	INTEL_GUC_RECV_IS_RESPONSE(x)	((u32)(x) >= INTEL_GUC_RECV_MASK)
> +#define	INTEL_GUC_RECV_STATUS(x)	(INTEL_GUC_RECV_MASK | (x))
>  
>  /* GUC will return status back to SOFT_SCRATCH_O_REG */
> -enum guc2host_status {
> -	GUC2HOST_STATUS_SUCCESS = GUC2HOST_STATUS(0x0),
> -	GUC2HOST_STATUS_ALLOCATE_DOORBELL_FAIL = GUC2HOST_STATUS(0x10),
> -	GUC2HOST_STATUS_DEALLOCATE_DOORBELL_FAIL = GUC2HOST_STATUS(0x20),
> -	GUC2HOST_STATUS_GENERIC_FAIL = GUC2HOST_STATUS(0x0000F000)
> +enum intel_guc_recv_status {
> +	INTEL_GUC_RECV_STATUS_SUCCESS = INTEL_GUC_RECV_STATUS(0x0),
> +	INTEL_GUC_RECV_STATUS_ALLOCATE_DOORBELL_FAIL =
> +					INTEL_GUC_RECV_STATUS(0x10),
> +	INTEL_GUC_RECV_STATUS_DEALLOCATE_DOORBELL_FAIL =
> +					INTEL_GUC_RECV_STATUS(0x20),
> +	INTEL_GUC_RECV_STATUS_GENERIC_FAIL =
> +					INTEL_GUC_RECV_STATUS(0x0000F000)
>  };

Looking at these, these are still ok as

enum intel_guc_action, enum intel_guc_status

>  /* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */
> -enum guc2host_message {
> -	GUC2HOST_MSG_CRASH_DUMP_POSTED = (1 << 1),
> -	GUC2HOST_MSG_FLUSH_LOG_BUFFER = (1 << 3)
> +enum intel_guc_recv_message {
> +	INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1),
> +	INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER = BIT(3)
>  };

Whereas this is ok as intel_guc_recv_message since it is quite
specialised.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre


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