[Intel-gfx] [PATCH v4 2/3] drm/i915/gen9: Fix PCODE polling during CDCLK change notification
Ville Syrjälä
ville.syrjala at linux.intel.com
Mon Nov 28 15:58:26 UTC 2016
On Mon, Nov 28, 2016 at 05:29:28PM +0200, Imre Deak wrote:
> commit 848496e5902833600f7992f4faa82dc1546051ba
> Author: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Date: Wed Jul 13 16:32:03 2016 +0300
>
> drm/i915: Wait up to 3ms for the pcu to ack the cdclk change request on SKL
>
> increased the timeout to match the spec, but we still see a timeout on
> at least one SKL. A CDCLK change request following the failed one will
> succeed nevertheless.
>
> I could reproduce this problem easily by running kms_pipe_crc_basic in a
> loop. In all failure cases _wait_for() was pre-empted for >3ms and so in
> the worst case - when the pre-emption happened right after calculating
> timeout__ in _wait_for() - we called skl_cdclk_wait_for_pcu_ready() only
> once which failed and so _wait_for() timed out. As opposed to this the
> spec says to keep retrying the request for at most a 3ms period.
>
> To fix this disable pre-emption to maximize the number of times we retry
> the request. Also increase the timeout to 10ms to account for interrupts
> that could reduce the number of these attempts. With this change I
> couldn't trigger the problem.
>
> v2:
> - Use 1ms poll period instead of 10us. (Chris)
> v3:
> - Poll with pre-emption disabled to increase the number of request
> attempts. (Ville, Chris)
> - Factor out a helper to poll, it's also needed by the next patch.
> v4:
> - Pass reply_mask, reply to skl_pcode_request(), instead of assuming the
> reply is generic. (Ville)
>
> Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Cc: Chris Wilson <chris at chris-wilson.co.uk>
> Reference: https://bugs.freedesktop.org/show_bug.cgi?id=97929
> Testcase: igt/kms_pipe_crc_basic/suspend-read-crc-pipe-B
> Signed-off-by: Imre Deak <imre.deak at intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/intel_display.c | 31 ++++++++---------------
> drivers/gpu/drm/i915/intel_pm.c | 49 ++++++++++++++++++++++++++++++++++++
> 3 files changed, 61 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 01f5067..1be5bab 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3593,6 +3593,8 @@ extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
>
> int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
> int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
> +int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
> + u32 reply_mask, u32 reply);
>
> /* intel_sideband.c */
> u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 5d11002..3d220da 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6245,35 +6245,24 @@ skl_dpll0_disable(struct drm_i915_private *dev_priv)
> dev_priv->cdclk_pll.vco = 0;
> }
>
> -static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
> -{
> - int ret;
> - u32 val;
> -
> - /* inform PCU we want to change CDCLK */
> - val = SKL_CDCLK_PREPARE_FOR_CHANGE;
> - mutex_lock(&dev_priv->rps.hw_lock);
> - ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
> - mutex_unlock(&dev_priv->rps.hw_lock);
> -
> - return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
> -}
> -
> -static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
> -{
> - return _wait_for(skl_cdclk_pcu_ready(dev_priv), 3000, 10) == 0;
> -}
> -
> static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
> {
> u32 freq_select, pcu_ack;
> + int ret;
>
> WARN_ON((cdclk == 24000) != (vco == 0));
>
> DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
>
> - if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
> - DRM_ERROR("failed to inform PCU about cdclk change\n");
> + mutex_lock(&dev_priv->rps.hw_lock);
> + ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
> + SKL_CDCLK_PREPARE_FOR_CHANGE,
> + SKL_CDCLK_READY_FOR_CHANGE,
> + SKL_CDCLK_READY_FOR_CHANGE);
> + mutex_unlock(&dev_priv->rps.hw_lock);
> + if (ret) {
> + DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
> + ret);
> return;
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 66c62f3..aed88e0 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7864,6 +7864,55 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
> return 0;
> }
>
> +static bool skl_pcode_try_request(struct drm_i915_private *dev_priv, u32 mbox,
> + u32 request, u32 reply_mask, u32 reply,
> + u32 *status)
> +{
> + u32 val = request;
> +
> + *status = sandybridge_pcode_read(dev_priv, mbox, &val);
> +
> + return *status || ((val & reply_mask) == reply);
> +}
> +
> +/**
> + * skl_pcode_request - send PCODE request until acknowledgment
> + * @dev_priv: device private
> + * @mbox: PCODE mailbox ID the request is targeted for
> + * @request: request ID
> + * @reply_mask: mask used to check for request acknowledgment
> + * @reply: value used to check for request acknowledgement
> + *
> + * Keep resending the @request to @mbox until PCODE acknowledges it, PCODE
> + * reports an error or a 10ms timeout expires. The request is acknowledged
> + * once the PCODE reply dword equals @reply after aplying @reply_mask.
> + *
> + * Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some
> + * other error as reported by PCODE.
> + */
> +int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
> + u32 reply_mask, u32 reply)
> +{
> + u32 status;
> + int ret;
> +
> + WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
> +
> + /*
> + * The spec says to keep retrying the request for at most 3ms until
This comment seems a little misplaced. The 3ms is specified for the
cdclk prep request, SAGV will have a different value.
If we don't want callers to pass in the timeout as well, I guess we'll
at least want to reword this comment to say which callers need what
kind of timeouts. Though I kinda like the idea of callers passing that
in as well.
> + * acknowledgement, so disable pre-emption to maximize the number of
> + * attempts within this duration. Use a 10ms overall timeout to
> + * account for interrupts that could reduce the number of attempts.
> + */
> + preempt_disable();
> + ret = wait_for_atomic(skl_pcode_try_request(dev_priv, mbox, request,
> + reply_mask, reply, &status),
> + 10);
> + preempt_enable();
> +
> + return ret ? ret : status;
> +}
> +
> static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
> {
> /*
> --
> 2.5.0
--
Ville Syrjälä
Intel OTC
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