[Intel-gfx] [PATCH 09/19] drm/i915: Make IS_BROADWELL only take dev_priv
David Weinehall
david.weinehall at linux.intel.com
Wed Oct 12 12:07:47 UTC 2016
On Tue, Oct 11, 2016 at 02:21:42PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
>
> Saves 1808 bytes of .rodata strings.
>
> v2: Add parantheses around dev_priv. (Ville Syrjala)
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
Reviewed-by: David Weinehall <david.weinehall at linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 6 ++++--
> drivers/gpu/drm/i915/i915_drv.h | 6 +++---
> drivers/gpu/drm/i915/i915_gem.c | 5 +++--
> drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
> drivers/gpu/drm/i915/intel_color.c | 4 ++--
> drivers/gpu/drm/i915/intel_display.c | 21 +++++++++++----------
> drivers/gpu/drm/i915/intel_dp.c | 19 ++++++++++---------
> drivers/gpu/drm/i915/intel_pm.c | 20 +++++++++++---------
> drivers/gpu/drm/i915/intel_psr.c | 4 ++--
> drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +--
> drivers/gpu/drm/i915/intel_sprite.c | 8 ++++----
> 11 files changed, 52 insertions(+), 46 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index f6ba8f262238..8899835fffab 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -189,13 +189,15 @@ static void intel_detect_pch(struct drm_device *dev)
> } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
> dev_priv->pch_type = PCH_LPT;
> DRM_DEBUG_KMS("Found LynxPoint PCH\n");
> - WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
> + WARN_ON(!IS_HASWELL(dev_priv) &&
> + !IS_BROADWELL(dev_priv));
> WARN_ON(IS_HSW_ULT(dev_priv) ||
> IS_BDW_ULT(dev_priv));
> } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
> dev_priv->pch_type = PCH_LPT;
> DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
> - WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
> + WARN_ON(!IS_HASWELL(dev_priv) &&
> + !IS_BROADWELL(dev_priv));
> WARN_ON(!IS_HSW_ULT(dev_priv) &&
> !IS_BDW_ULT(dev_priv));
> } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 3f321932d18a..13e409554fcc 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2662,7 +2662,7 @@ struct drm_i915_cmd_table {
> #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
> #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
> #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
> -#define IS_BROADWELL(dev) (INTEL_INFO(dev)->is_broadwell)
> +#define IS_BROADWELL(dev_priv) ((dev_priv)->info.is_broadwell)
> #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
> #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
> #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
> @@ -2769,8 +2769,8 @@ struct drm_i915_cmd_table {
> #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
> #define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop)
> #define HAS_EDRAM(dev) (!!(__I915__(dev)->edram_cap & EDRAM_ENABLED))
> -#define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
> - HAS_EDRAM(dev))
> +#define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
> + IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
> #define HWS_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->hws_needs_physical)
>
> #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->has_hw_contexts)
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 6da841500510..aefb88f987b2 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -3473,7 +3473,7 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
> level = I915_CACHE_LLC;
> break;
> case I915_CACHING_DISPLAY:
> - level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
> + level = HAS_WT(dev_priv) ? I915_CACHE_WT : I915_CACHE_NONE;
> break;
> default:
> return -EINVAL;
> @@ -3531,7 +3531,8 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
> * with that bit in the PTE to main memory with just one PIPE_CONTROL.
> */
> ret = i915_gem_object_set_cache_level(obj,
> - HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
> + HAS_WT(to_i915(obj->base.dev)) ?
> + I915_CACHE_WT : I915_CACHE_NONE);
> if (ret) {
> vma = ERR_PTR(ret);
> goto err_unpin_display;
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 0bb4232f66bc..0f8f073c589c 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2129,7 +2129,7 @@ static void gtt_write_workarounds(struct drm_device *dev)
> * workarounds here even if they get overwritten by GPU reset.
> */
> /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt */
> - if (IS_BROADWELL(dev))
> + if (IS_BROADWELL(dev_priv))
> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
> else if (IS_CHERRYVIEW(dev))
> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index 5362c07932d3..be76ef88678c 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -540,8 +540,8 @@ void intel_color_init(struct drm_crtc *crtc)
> } else if (IS_HASWELL(dev)) {
> dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
> dev_priv->display.load_luts = haswell_load_luts;
> - } else if (IS_BROADWELL(dev) || IS_SKYLAKE(dev) ||
> - IS_BROXTON(dev) || IS_KABYLAKE(dev)) {
> + } else if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv) ||
> + IS_BROXTON(dev_priv) || IS_KABYLAKE(dev_priv)) {
> dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
> dev_priv->display.load_luts = broadwell_load_luts;
> } else {
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 7894675bfcb8..d159a315099f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3139,7 +3139,7 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
> dspcntr = DISPPLANE_GAMMA_ENABLE;
> dspcntr |= DISPLAY_PLANE_ENABLE;
>
> - if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
>
> switch (fb->pixel_format) {
> @@ -3168,7 +3168,7 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
> if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
> dspcntr |= DISPPLANE_TILED;
>
> - if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
> + if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv))
> dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
>
> intel_add_fb_offsets(&x, &y, plane_state, 0);
> @@ -3179,7 +3179,7 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
> if (rotation == DRM_ROTATE_180) {
> dspcntr |= DISPPLANE_ROTATE_180;
>
> - if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
> + if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
> x += (crtc_state->pipe_src_w - 1);
> y += (crtc_state->pipe_src_h - 1);
> }
> @@ -3196,7 +3196,7 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
> I915_WRITE(DSPSURF(plane),
> intel_fb_gtt_offset(fb, rotation) +
> intel_crtc->dspaddr_offset);
> - if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
> + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
> } else {
> I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
> @@ -4879,7 +4879,7 @@ void hsw_enable_ips(struct intel_crtc *crtc)
> */
>
> assert_plane_enabled(dev_priv, crtc->plane);
> - if (IS_BROADWELL(dev)) {
> + if (IS_BROADWELL(dev_priv)) {
> mutex_lock(&dev_priv->rps.hw_lock);
> WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
> mutex_unlock(&dev_priv->rps.hw_lock);
> @@ -4911,7 +4911,7 @@ void hsw_disable_ips(struct intel_crtc *crtc)
> return;
>
> assert_plane_enabled(dev_priv, crtc->plane);
> - if (IS_BROADWELL(dev)) {
> + if (IS_BROADWELL(dev_priv)) {
> mutex_lock(&dev_priv->rps.hw_lock);
> WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
> mutex_unlock(&dev_priv->rps.hw_lock);
> @@ -5854,7 +5854,7 @@ static void intel_update_max_cdclk(struct drm_device *dev)
> dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
> } else if (IS_BROXTON(dev)) {
> dev_priv->max_cdclk_freq = 624000;
> - } else if (IS_BROADWELL(dev)) {
> + } else if (IS_BROADWELL(dev_priv)) {
> /*
> * FIXME with extra cooling we can allow
> * 540 MHz for ULX and 675 Mhz for ULT.
> @@ -7023,6 +7023,7 @@ static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
> static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
> struct intel_crtc_state *pipe_config)
> {
> + struct drm_i915_private *dev_priv = to_i915(dev);
> struct drm_atomic_state *state = pipe_config->base.state;
> struct intel_crtc *other_crtc;
> struct intel_crtc_state *other_crtc_state;
> @@ -7035,7 +7036,7 @@ static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
> return -EINVAL;
> }
>
> - if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
> + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> if (pipe_config->fdi_lanes > 2) {
> DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
> pipe_config->fdi_lanes);
> @@ -9883,7 +9884,7 @@ ironlake_get_initial_plane_config(struct intel_crtc *crtc,
> fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
>
> base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
> - if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
> + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> offset = I915_READ(DSPOFFSET(pipe));
> } else {
> if (plane_config->tiling)
> @@ -17244,7 +17245,7 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m,
> return;
>
> err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
> - if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> err_printf(m, "PWR_WELL_CTL2: %08x\n",
> error->power_well_driver);
> for_each_pipe(dev_priv, i) {
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 2e06dfb64bd4..02e74c467a55 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -821,15 +821,16 @@ static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
> uint32_t aux_clock_divider)
> {
> struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> - struct drm_device *dev = intel_dig_port->base.base.dev;
> + struct drm_i915_private *dev_priv =
> + to_i915(intel_dig_port->base.base.dev);
> uint32_t precharge, timeout;
>
> - if (IS_GEN6(dev))
> + if (IS_GEN6(dev_priv))
> precharge = 3;
> else
> precharge = 5;
>
> - if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A)
> + if (IS_BROADWELL(dev_priv) && intel_dig_port->port == PORT_A)
> timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
> else
> timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
> @@ -2999,10 +3000,10 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
> uint8_t
> intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
> {
> - struct drm_device *dev = intel_dp_to_dev(intel_dp);
> + struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
> enum port port = dp_to_dig_port(intel_dp)->port;
>
> - if (INTEL_INFO(dev)->gen >= 9) {
> + if (INTEL_GEN(dev_priv) >= 9) {
> switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
> case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
> return DP_TRAIN_PRE_EMPH_LEVEL_3;
> @@ -3015,7 +3016,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
> default:
> return DP_TRAIN_PRE_EMPH_LEVEL_0;
> }
> - } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
> + } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
> case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
> return DP_TRAIN_PRE_EMPH_LEVEL_3;
> @@ -3027,7 +3028,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
> default:
> return DP_TRAIN_PRE_EMPH_LEVEL_0;
> }
> - } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> + } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
> case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
> return DP_TRAIN_PRE_EMPH_LEVEL_3;
> @@ -3039,7 +3040,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
> default:
> return DP_TRAIN_PRE_EMPH_LEVEL_0;
> }
> - } else if (IS_GEN7(dev) && port == PORT_A) {
> + } else if (IS_GEN7(dev_priv) && port == PORT_A) {
> switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
> case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
> return DP_TRAIN_PRE_EMPH_LEVEL_2;
> @@ -5648,7 +5649,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
> /* intel_dp vfuncs */
> if (INTEL_INFO(dev)->gen >= 9)
> intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
> - else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> + else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
> else if (HAS_PCH_SPLIT(dev_priv))
> intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 9155735d01df..3ba9502cf2c2 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2157,7 +2157,7 @@ static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
> }
> }
>
> - } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
> + } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> uint64_t sskpd = I915_READ64(MCH_SSKPD);
>
> wm[0] = (sskpd >> 56) & 0xFF;
> @@ -2205,12 +2205,14 @@ static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
>
> int ilk_wm_max_level(const struct drm_device *dev)
> {
> + struct drm_i915_private *dev_priv = to_i915(dev);
> +
> /* how many WM levels are we expecting */
> - if (INTEL_INFO(dev)->gen >= 9)
> + if (INTEL_GEN(dev_priv) >= 9)
> return 7;
> - else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> + else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> return 4;
> - else if (INTEL_INFO(dev)->gen >= 6)
> + else if (INTEL_GEN(dev_priv) >= 6)
> return 3;
> else
> return 2;
> @@ -2393,7 +2395,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
> memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
> pipe_wm->wm[0] = pipe_wm->raw_wm[0];
>
> - if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
>
> if (!ilk_validate_pipe_wm(dev, pipe_wm))
> @@ -2580,7 +2582,7 @@ static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
>
> - if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> return 2 * level;
> else
> return dev_priv->wm.pri_latency[level];
> @@ -2804,7 +2806,7 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
> I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
>
> if (dirty & WM_DIRTY_DDB) {
> - if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
> + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> val = I915_READ(WM_MISC);
> if (results->partitioning == INTEL_DDB_PART_1_2)
> val &= ~WM_MISC_DATA_PARTITION_5_6;
> @@ -4407,7 +4409,7 @@ static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
> };
>
> hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
> - if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
>
> memset(active, 0, sizeof(*active));
> @@ -4615,7 +4617,7 @@ void ilk_wm_get_hw_state(struct drm_device *dev)
> hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
> }
>
> - if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
> INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
> else if (IS_IVYBRIDGE(dev_priv))
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 9e2fbac9776e..d0667f9d9178 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -827,14 +827,14 @@ void intel_psr_init(struct drm_device *dev)
>
> /* Per platform default */
> if (i915.enable_psr == -1) {
> - if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> i915.enable_psr = 1;
> else
> i915.enable_psr = 0;
> }
>
> /* Set link_standby x link_off defaults */
> - if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> /* HSW and BDW require workarounds that we don't implement. */
> dev_priv->psr.link_standby = false;
> else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index ed1faf14f777..77ef03cb6163 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -288,7 +288,6 @@ void intel_display_set_init_power(struct drm_i915_private *dev_priv,
> static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
> {
> struct pci_dev *pdev = dev_priv->drm.pdev;
> - struct drm_device *dev = &dev_priv->drm;
>
> /*
> * After we re-enable the power well, if we touch VGA register 0x3d5
> @@ -304,7 +303,7 @@ static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
> outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
> vga_put(pdev, VGA_RSRC_LEGACY_IO);
>
> - if (IS_BROADWELL(dev))
> + if (IS_BROADWELL(dev_priv))
> gen8_irq_power_well_post_enable(dev_priv,
> 1 << PIPE_C | 1 << PIPE_B);
> }
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index d0f798ce6bb2..fefd3034aead 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -542,12 +542,12 @@ ivb_update_plane(struct drm_plane *plane,
> if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
> sprctl |= SPRITE_TILED;
>
> - if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE;
> else
> sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
>
> - if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> sprctl |= SPRITE_PIPE_CSC_ENABLE;
>
> /* Sizes are 0 based */
> @@ -566,7 +566,7 @@ ivb_update_plane(struct drm_plane *plane,
> sprctl |= SPRITE_ROTATE_180;
>
> /* HSW and BDW does this automagically in hardware */
> - if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
> + if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
> x += src_w;
> y += src_h;
> }
> @@ -590,7 +590,7 @@ ivb_update_plane(struct drm_plane *plane,
>
> /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
> * register */
> - if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
> else if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
> I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
> --
> 2.7.4
>
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