[Intel-gfx] [PATCH] drm/i915: Fix mismatched INIT power domain disabling during suspend

Imre Deak imre.deak at intel.com
Thu Oct 13 16:59:17 UTC 2016


On to, 2016-10-13 at 15:21 +0300, Jani Nikula wrote:
> On Thu, 13 Oct 2016, Imre Deak <imre.deak at intel.com> wrote:
> > Currently the display INIT power domain disabling/enabling happens in a
> > mismatched way in the suspend/resume_early hooks respectively. This can
> > leave display power wells incorrectly disabled in the resume hook if the
> > suspend sequence is aborted for some reason resulting in the
> > suspend/resume hooks getting called but the suspend_late/resume_early
> > hooks being skipped. In particular this change fixes "Unclaimed read
> > from register 0x1e1204" on BYT/BSW triggered from i915_drm_resume()->
> > intel_pps_unlock_regs_wa() when suspending with /sys/power/pm_test set
> > to devices.
> > 
> > Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > Cc: David Weinehall <david.weinehall at intel.com>
> > Signed-off-by: Imre Deak <imre.deak at intel.com>
> 
> Fixes: ?

Fixes: 85e90679335f ("drm/i915: disable power wells on suspend")

> Cc: stable at vger.kernel.org ?

It matters only for an error path which is rare (another device needs
to fail suspending between its suspend and suspend_late steps) and
pm_test. So I'd say this isn't for fixes or stable.

--Imre

> 
> > ---
> >  drivers/gpu/drm/i915/i915_drv.c | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c
> > b/drivers/gpu/drm/i915/i915_drv.c
> > index e9b3bfc..5adabac 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -1430,8 +1430,6 @@ static int i915_drm_suspend(struct drm_device
> > *dev)
> >  
> >  	dev_priv->suspend_count++;
> >  
> > -	intel_display_set_init_power(dev_priv, false);
> > -
> >  	intel_csr_ucode_suspend(dev_priv);
> >  
> >  out:
> > @@ -1449,6 +1447,8 @@ static int i915_drm_suspend_late(struct
> > drm_device *dev, bool hibernation)
> >  
> >  	disable_rpm_wakeref_asserts(dev_priv);
> >  
> > +	intel_display_set_init_power(dev_priv, false);
> > +
> >  	fw_csr = !IS_BROXTON(dev_priv) &&
> >  		suspend_to_idle(dev_priv) && dev_priv-
> > >csr.dmc_payload;
> >  	/*
> 


More information about the Intel-gfx mailing list