[Intel-gfx] [drm-intel:drm-intel-next-queued 1/1] drivers/gpu/drm/i915/gvt/handlers.c:137:3: note: in expansion of macro 'if'

kbuild test robot fengguang.wu at intel.com
Mon Oct 17 21:04:39 UTC 2016


tree:   git://anongit.freedesktop.org/drm-intel drm-intel-next-queued
head:   06a75ace46e2fdd1d93b06228df0e2dfe526cc27
commit: 06a75ace46e2fdd1d93b06228df0e2dfe526cc27 [1/1] Merge tag 'gvt-next-2016-10-14' of https://github.com/01org/gvt-linux into drm-intel-next-queued
config: x86_64-randconfig-a0-10171253 (attached as .config)
compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
reproduce:
        git checkout 06a75ace46e2fdd1d93b06228df0e2dfe526cc27
        # save the attached .config to linux build tree
        make ARCH=x86_64 

All warnings (new ones prefixed by >>):

   In file included from include/uapi/linux/stddef.h:1:0,
                    from include/linux/stddef.h:4,
                    from include/uapi/linux/posix_types.h:4,
                    from include/uapi/linux/types.h:13,
                    from include/linux/types.h:5,
                    from include/uapi/drm/drm.h:41,
                    from include/uapi/drm/i915_drm.h:30,
                    from drivers/gpu/drm/i915/i915_drv.h:33,
                    from drivers/gpu/drm/i915/gvt/handlers.c:39:
   drivers/gpu/drm/i915/gvt/handlers.c: In function 'render_mmio_to_ring_id':
   drivers/gpu/drm/i915/gvt/handlers.c:137:31: error: 'gvt->dev_priv->engine[i]' is a pointer; did you mean to use '->'?
      if (gvt->dev_priv->engine[i].mmio_base == reg)
                                  ^
      ->
   include/linux/compiler.h:149:30: note: in definition of macro '__trace_if'
     if (__builtin_constant_p(!!(cond)) ? !!(cond) :   \
                                 ^~~~
>> drivers/gpu/drm/i915/gvt/handlers.c:137:3: note: in expansion of macro 'if'
      if (gvt->dev_priv->engine[i].mmio_base == reg)
      ^~
   drivers/gpu/drm/i915/gvt/handlers.c:137:31: error: 'gvt->dev_priv->engine[i]' is a pointer; did you mean to use '->'?
      if (gvt->dev_priv->engine[i].mmio_base == reg)
                                  ^
      ->
   include/linux/compiler.h:149:42: note: in definition of macro '__trace_if'
     if (__builtin_constant_p(!!(cond)) ? !!(cond) :   \
                                             ^~~~
>> drivers/gpu/drm/i915/gvt/handlers.c:137:3: note: in expansion of macro 'if'
      if (gvt->dev_priv->engine[i].mmio_base == reg)
      ^~
   drivers/gpu/drm/i915/gvt/handlers.c:137:31: error: 'gvt->dev_priv->engine[i]' is a pointer; did you mean to use '->'?
      if (gvt->dev_priv->engine[i].mmio_base == reg)
                                  ^
      ->
   include/linux/compiler.h:160:16: note: in definition of macro '__trace_if'
      ______r = !!(cond);     \
                   ^~~~
>> drivers/gpu/drm/i915/gvt/handlers.c:137:3: note: in expansion of macro 'if'
      if (gvt->dev_priv->engine[i].mmio_base == reg)
      ^~

vim +/if +137 drivers/gpu/drm/i915/gvt/handlers.c

12d14cc4 Zhi Wang 2016-08-30   33   *    Ping Gao <ping.a.gao at intel.com>
12d14cc4 Zhi Wang 2016-08-30   34   *    Zhi Wang <zhi.a.wang at intel.com>
12d14cc4 Zhi Wang 2016-08-30   35   *
12d14cc4 Zhi Wang 2016-08-30   36  
12d14cc4 Zhi Wang 2016-08-30   37   */
12d14cc4 Zhi Wang 2016-08-30   38  
12d14cc4 Zhi Wang 2016-08-30  @39  #include "i915_drv.h"
12d14cc4 Zhi Wang 2016-08-30   40  
e39c5add Zhi Wang 2016-09-02   41  /* XXX FIXME i915 has changed PP_XXX definition */
e39c5add Zhi Wang 2016-09-02   42  #define PCH_PP_STATUS  _MMIO(0xc7200)
e39c5add Zhi Wang 2016-09-02   43  #define PCH_PP_CONTROL _MMIO(0xc7204)
e39c5add Zhi Wang 2016-09-02   44  #define PCH_PP_ON_DELAYS _MMIO(0xc7208)
e39c5add Zhi Wang 2016-09-02   45  #define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
e39c5add Zhi Wang 2016-09-02   46  #define PCH_PP_DIVISOR _MMIO(0xc7210)
e39c5add Zhi Wang 2016-09-02   47  
12d14cc4 Zhi Wang 2016-08-30   48  /* Register contains RO bits */
12d14cc4 Zhi Wang 2016-08-30   49  #define F_RO		(1 << 0)
12d14cc4 Zhi Wang 2016-08-30   50  /* Register contains graphics address */
12d14cc4 Zhi Wang 2016-08-30   51  #define F_GMADR		(1 << 1)
12d14cc4 Zhi Wang 2016-08-30   52  /* Mode mask registers with high 16 bits as the mask bits */
12d14cc4 Zhi Wang 2016-08-30   53  #define F_MODE_MASK	(1 << 2)
12d14cc4 Zhi Wang 2016-08-30   54  /* This reg can be accessed by GPU commands */
12d14cc4 Zhi Wang 2016-08-30   55  #define F_CMD_ACCESS	(1 << 3)
12d14cc4 Zhi Wang 2016-08-30   56  /* This reg has been accessed by a VM */
12d14cc4 Zhi Wang 2016-08-30   57  #define F_ACCESSED	(1 << 4)
12d14cc4 Zhi Wang 2016-08-30   58  /* This reg has been accessed through GPU commands */
12d14cc4 Zhi Wang 2016-08-30   59  #define F_CMD_ACCESSED	(1 << 5)
12d14cc4 Zhi Wang 2016-08-30   60  /* This reg could be accessed by unaligned address */
12d14cc4 Zhi Wang 2016-08-30   61  #define F_UNALIGN	(1 << 6)
12d14cc4 Zhi Wang 2016-08-30   62  
12d14cc4 Zhi Wang 2016-08-30   63  unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt)
12d14cc4 Zhi Wang 2016-08-30   64  {
12d14cc4 Zhi Wang 2016-08-30   65  	if (IS_BROADWELL(gvt->dev_priv))
12d14cc4 Zhi Wang 2016-08-30   66  		return D_BDW;
12d14cc4 Zhi Wang 2016-08-30   67  	else if (IS_SKYLAKE(gvt->dev_priv))
12d14cc4 Zhi Wang 2016-08-30   68  		return D_SKL;
12d14cc4 Zhi Wang 2016-08-30   69  
12d14cc4 Zhi Wang 2016-08-30   70  	return 0;
12d14cc4 Zhi Wang 2016-08-30   71  }
12d14cc4 Zhi Wang 2016-08-30   72  
12d14cc4 Zhi Wang 2016-08-30   73  bool intel_gvt_match_device(struct intel_gvt *gvt,
12d14cc4 Zhi Wang 2016-08-30   74  		unsigned long device)
12d14cc4 Zhi Wang 2016-08-30   75  {
12d14cc4 Zhi Wang 2016-08-30   76  	return intel_gvt_get_device_type(gvt) & device;
12d14cc4 Zhi Wang 2016-08-30   77  }
12d14cc4 Zhi Wang 2016-08-30   78  
e39c5add Zhi Wang 2016-09-02   79  static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset,
e39c5add Zhi Wang 2016-09-02   80  	void *p_data, unsigned int bytes)
e39c5add Zhi Wang 2016-09-02   81  {
e39c5add Zhi Wang 2016-09-02   82  	memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
e39c5add Zhi Wang 2016-09-02   83  }
e39c5add Zhi Wang 2016-09-02   84  
e39c5add Zhi Wang 2016-09-02   85  static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset,
e39c5add Zhi Wang 2016-09-02   86  	void *p_data, unsigned int bytes)
e39c5add Zhi Wang 2016-09-02   87  {
e39c5add Zhi Wang 2016-09-02   88  	memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
e39c5add Zhi Wang 2016-09-02   89  }
e39c5add Zhi Wang 2016-09-02   90  
12d14cc4 Zhi Wang 2016-08-30   91  static int new_mmio_info(struct intel_gvt *gvt,
12d14cc4 Zhi Wang 2016-08-30   92  		u32 offset, u32 flags, u32 size,
12d14cc4 Zhi Wang 2016-08-30   93  		u32 addr_mask, u32 ro_mask, u32 device,
12d14cc4 Zhi Wang 2016-08-30   94  		void *read, void *write)
12d14cc4 Zhi Wang 2016-08-30   95  {
12d14cc4 Zhi Wang 2016-08-30   96  	struct intel_gvt_mmio_info *info, *p;
12d14cc4 Zhi Wang 2016-08-30   97  	u32 start, end, i;
12d14cc4 Zhi Wang 2016-08-30   98  
12d14cc4 Zhi Wang 2016-08-30   99  	if (!intel_gvt_match_device(gvt, device))
12d14cc4 Zhi Wang 2016-08-30  100  		return 0;
12d14cc4 Zhi Wang 2016-08-30  101  
12d14cc4 Zhi Wang 2016-08-30  102  	if (WARN_ON(!IS_ALIGNED(offset, 4)))
12d14cc4 Zhi Wang 2016-08-30  103  		return -EINVAL;
12d14cc4 Zhi Wang 2016-08-30  104  
12d14cc4 Zhi Wang 2016-08-30  105  	start = offset;
12d14cc4 Zhi Wang 2016-08-30  106  	end = offset + size;
12d14cc4 Zhi Wang 2016-08-30  107  
12d14cc4 Zhi Wang 2016-08-30  108  	for (i = start; i < end; i += 4) {
12d14cc4 Zhi Wang 2016-08-30  109  		info = kzalloc(sizeof(*info), GFP_KERNEL);
12d14cc4 Zhi Wang 2016-08-30  110  		if (!info)
12d14cc4 Zhi Wang 2016-08-30  111  			return -ENOMEM;
12d14cc4 Zhi Wang 2016-08-30  112  
12d14cc4 Zhi Wang 2016-08-30  113  		info->offset = i;
12d14cc4 Zhi Wang 2016-08-30  114  		p = intel_gvt_find_mmio_info(gvt, info->offset);
12d14cc4 Zhi Wang 2016-08-30  115  		if (p)
12d14cc4 Zhi Wang 2016-08-30  116  			gvt_err("dup mmio definition offset %x\n",
12d14cc4 Zhi Wang 2016-08-30  117  				info->offset);
12d14cc4 Zhi Wang 2016-08-30  118  		info->size = size;
12d14cc4 Zhi Wang 2016-08-30  119  		info->length = (i + 4) < end ? 4 : (end - i);
12d14cc4 Zhi Wang 2016-08-30  120  		info->addr_mask = addr_mask;
12d14cc4 Zhi Wang 2016-08-30  121  		info->device = device;
e39c5add Zhi Wang 2016-09-02  122  		info->read = read ? read : intel_vgpu_default_mmio_read;
e39c5add Zhi Wang 2016-09-02  123  		info->write = write ? write : intel_vgpu_default_mmio_write;
12d14cc4 Zhi Wang 2016-08-30  124  		gvt->mmio.mmio_attribute[info->offset / 4] = flags;
12d14cc4 Zhi Wang 2016-08-30  125  		INIT_HLIST_NODE(&info->node);
12d14cc4 Zhi Wang 2016-08-30  126  		hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset);
12d14cc4 Zhi Wang 2016-08-30  127  	}
12d14cc4 Zhi Wang 2016-08-30  128  	return 0;
12d14cc4 Zhi Wang 2016-08-30  129  }
12d14cc4 Zhi Wang 2016-08-30  130  
28c4c6ca Zhi Wang 2016-05-01  131  static int render_mmio_to_ring_id(struct intel_gvt *gvt, unsigned int reg)
28c4c6ca Zhi Wang 2016-05-01  132  {
28c4c6ca Zhi Wang 2016-05-01  133  	int i;
28c4c6ca Zhi Wang 2016-05-01  134  
28c4c6ca Zhi Wang 2016-05-01  135  	reg &= ~GENMASK(11, 0);
28c4c6ca Zhi Wang 2016-05-01  136  	for (i = 0; i < I915_NUM_ENGINES; i++) {
28c4c6ca Zhi Wang 2016-05-01 @137  		if (gvt->dev_priv->engine[i].mmio_base == reg)
28c4c6ca Zhi Wang 2016-05-01  138  			return i;
28c4c6ca Zhi Wang 2016-05-01  139  	}
28c4c6ca Zhi Wang 2016-05-01  140  	return -1;

:::::: The code at line 137 was first introduced by commit
:::::: 28c4c6ca7f794b2d5ac8773d43311e95f6518415 drm/i915/gvt: vGPU workload submission

:::::: TO: Zhi Wang <zhi.a.wang at intel.com>
:::::: CC: Zhenyu Wang <zhenyuw at linux.intel.com>

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation
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