[Intel-gfx] [PATCH v3] kms_atomic : Added subtest for Single Pipe DBUF validation

[Daniel Vetter]

On Wed, Oct 26, 2016 at 09:33:27AM +0530, meghanelogal wrote:
> Existing DDB algorithm divide the DDB wrt data rate,
> hence the planes with the less height but same width
> will be allocated less blocks and watermark are based
> on width which requires more DDB. With this data the flip
> may fail.
> 
> In new DDB algorithm, the DDB is divided based on
> watermark requirement.
> 
> In this subtest, dividing the htotal/200 will allocate
> ~2-4 blocks out of total(512/896), flip may fail with the
> exisiting algorithm.But with the new algorithm it will pass.
> 
> Signed-off-by: Megha Nelogal <megha.i.nelogal at intel.com>

When resending pls at least mention what you've changed in some per-patch
changelog. And maybe address the stuff I've been raising, but this way
your patch just won't land.
-Daniel
> ---
>  tests/kms_atomic.c | 79 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 79 insertions(+)
> 
> diff --git a/tests/kms_atomic.c b/tests/kms_atomic.c
> index f27ee46..3ab1d3f 100644
> --- a/tests/kms_atomic.c
> +++ b/tests/kms_atomic.c
> @@ -1280,6 +1280,60 @@ static void atomic_invalid_params(struct kms_atomic_crtc_state *crtc,
>  	do_ioctl_err(desc->fd, DRM_IOCTL_MODE_ATOMIC, &ioc, EFAULT);
>  }
>  
> +static void validate_dbuf(struct kms_atomic_crtc_state *crtc,
> +				struct kms_atomic_plane_state **plane_array,
> +				int plane_count)
> +{
> +	int i;
> +	struct kms_atomic_desc *desc = crtc->state->desc;
> +
> +	/* for active crtc do modeset on the native resolution */
> +	drmModeAtomicReq *req = drmModeAtomicAlloc();
> +	struct drm_mode_modeinfo *mode = crtc->mode.data;
> +	struct kms_atomic_plane_state plane;
> +	struct igt_fb fb;
> +
> +	crtc_populate_req(crtc, req);
> +
> +	/* Add plane data to the structure...*/
> +	uint32_t crtc_x = 0;
> +	uint32_t crtc_y = 0;
> +
> +	for (i = 0; i < plane_count; i++) {
> +		plane = *plane_array[i];
> +		uint32_t format = plane_get_igt_format(&plane);
> +
> +		igt_require(format != 0);
> +		plane.src_x = 0;
> +		plane.src_y = 0;
> +		plane.src_w = (mode->hdisplay / (1)) << 16;
> +		plane.crtc_x = crtc_x;
> +		plane.crtc_y = crtc_y;
> +		plane.crtc_w = (mode->hdisplay) / (1);
> +		plane.crtc_h = (mode->vdisplay) / (i + 1);
> +
> +		plane.crtc_id = crtc->obj;
> +
> +		if (i%2 == 0) {
> +			plane.src_h = (mode->vdisplay / (1)) << 16;
> +			plane.crtc_h = (mode->vdisplay) / (1);
> +		}
> +
> +		if (i%2 == 1) {
> +			plane.src_h = ceil((mode->vdisplay / 200) << 16);
> +			plane.crtc_h = ceil((mode->vdisplay / 200));
> +		}
> +
> +		plane.fb_id = igt_create_fb(plane.state->desc->fd,
> +						plane.crtc_w, plane.crtc_h,
> +						format, I915_TILING_NONE, &fb);
> +		plane_populate_req(&plane, req);
> +	}
> +	do_atomic_commit(desc->fd, req, ATOMIC_RELAX_NONE);
> +	drmModeAtomicFree(req);
> +}
> +
> +
>  igt_main
>  {
>  	struct kms_atomic_desc desc;
> @@ -1373,6 +1427,31 @@ igt_main
>  		atomic_state_free(scratch);
>  	}
>  
> +	igt_subtest("validate_dbuf") {
> +		int gen;
> +
> +		gen = intel_gen(intel_get_drm_devid(desc.fd));
> +		igt_require(gen >= 9);
> +
> +		struct kms_atomic_state *scratch = atomic_state_dup(current);
> +		struct kms_atomic_crtc_state *crtc;
> +		struct kms_atomic_plane_state *planes[2];
> +
> +		crtc = find_crtc(scratch, true);
> +		igt_require(crtc);
> +
> +		igt_require(find_connector(scratch, crtc));
> +
> +		planes[0] = find_plane(scratch, PLANE_TYPE_PRIMARY, crtc);
> +		igt_require(planes[0]);
> +
> +		planes[1] = find_plane(scratch, PLANE_TYPE_OVERLAY, crtc);
> +		igt_require(planes[1]);
> +
> +		validate_dbuf(crtc, planes, 2);
> +		atomic_state_free(scratch);
> +	}
> +
>  	atomic_state_free(current);
>  
>  	igt_fixture
> -- 
> 1.9.1
> 

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch