[Intel-gfx] [PATCH 00/14] Enable Upfront Link Training on DDI platforms

[Manasi Navare]

This patch series enables upfront link training on DDI platforms
(SKL/BDW/HSW/BXT) for DP SST and MST.
They are based on some of the patches submitted earlier by
Ander and Durgadoss.

The upfront link training had to be factored out of long pulse
hanlder because of deadlock issues seen on DP MST cases.
Now the upfront link training takes place in intel_dp_mode_valid()
to find the maximum lane count and link rate at which the DP link
can be successfully trained. These values are used to prune the
invalid modes before modeset. Modeset makes use the upfront lane
count and link train values.

These patches have been validated for DP SST on DDI platforms
(SKL/HSW/BDW/BXT). They have also been tested for any regressions
on non DDI platforms (CHV). 

The existing implementation of link training does not implement fallback
for link rate/lane count as per the DP spec.
This patch series adds fixes to the clock recovery and
Channel EQ sequences according to the DP Spec.
It also implements fallback loop to lower link rate
and lane count on CR and/or Channel EQ failures during link training.

Ander Conselvan de Oliveira (2):
  drm/i915: Don't pass crtc_state to intel_dp_set_link_params()
  drm/i915: Remove ddi_pll_sel from intel_crtc_state

Dhinakaran Pandiyan (2):
  drm/i915/dp: Move max. vswing check to it's own function
  drm/dp/i915: Make clock recovery in the link training compliant with
    DP Spec 1.2

Durgadoss R (2):
  drm/i915: Split bxt_ddi_pll_select()
  drm/i915/dp: Enable Upfront link training for typeC DP support on
    HSW/BDW/SKL/BXT (DDI platforms)

Jim Bride (3):
  drm/i915: Split skl_get_dpll()
  drm/i915/dp: Add a standalone function to obtain shared dpll for
    HSW/BDW/SKL/BXT
  drm/i915/dp/mst: Add support for upfront link training for DP MST

Manasi Navare (5):
  drm/i915: Split intel_ddi_pre_enable() into DP and HDMI versions
  drm/i915: Split hsw_get_dpll()
  drm/i915: Make DP link training channel equalization DP 1.2 Spec
    compliant
  drm/i915: Fallback to lower link rate and lane count during link
    training
  drm/i915: Reverse the loop in intel_dp_compute_config

 drivers/gpu/drm/i915/intel_ddi.c              | 283 +++++++++++++---
 drivers/gpu/drm/i915/intel_display.c          |  43 +--
 drivers/gpu/drm/i915/intel_dp.c               | 400 ++++++++++++++++-------
 drivers/gpu/drm/i915/intel_dp_link_training.c | 141 ++++----
 drivers/gpu/drm/i915/intel_dp_mst.c           |  71 +++-
 drivers/gpu/drm/i915/intel_dpll_mgr.c         | 454 ++++++++++++++++----------
 drivers/gpu/drm/i915/intel_dpll_mgr.h         |  15 +
 drivers/gpu/drm/i915/intel_drv.h              |  34 +-
 8 files changed, 973 insertions(+), 468 deletions(-)

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1.9.1