[Intel-gfx] [PATCH v4 21/25] drm/i915/slpc: Update freq min/max softlimits

[Sagar Arun Kamble]

v2: Removing checks for vma obj and kmap_atomic validity. (Chris)

v3: Rebase.

v4: Updated to make sure SLPC enable keeps min/max freq softlimits
    unchanged after initializing once. (Chris)

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble at intel.com>
---
 drivers/gpu/drm/i915/intel_slpc.c | 47 +++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h |  1 +
 2 files changed, 48 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 60b3aaf..1a3a515 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -269,6 +269,7 @@ void intel_slpc_init(struct drm_i915_private *dev_priv)
 	}
 
 	slpc_shared_data_init(dev_priv);
+	dev_priv->guc.slpc.first_enable = false;
 }
 
 void intel_slpc_cleanup(struct drm_i915_private *dev_priv)
@@ -279,6 +280,8 @@ void intel_slpc_cleanup(struct drm_i915_private *dev_priv)
 	mutex_lock(&dev_priv->drm.struct_mutex);
 	i915_vma_unpin_and_release(&guc->slpc.vma);
 	mutex_unlock(&dev_priv->drm.struct_mutex);
+
+	dev_priv->guc.slpc.first_enable = false;
 }
 
 void intel_slpc_suspend(struct drm_i915_private *dev_priv)
@@ -339,4 +342,48 @@ void intel_slpc_enable(struct drm_i915_private *dev_priv)
 	intel_slpc_set_param(dev_priv,
 			     SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE,
 			     0);
+
+	if (!dev_priv->guc.slpc.first_enable) {
+		struct drm_i915_gem_object *obj;
+		void *pv = NULL;
+		struct slpc_shared_data data;
+
+		obj = dev_priv->guc.slpc.vma->obj;
+		intel_slpc_query_task_state(dev_priv);
+
+		pv = kmap_atomic(i915_gem_object_get_page(obj, 0));
+		data = *(struct slpc_shared_data *) pv;
+		kunmap_atomic(pv);
+
+		/*
+		 * TODO: Define separate variables for slice and unslice
+		 *	 frequencies for driver state variable.
+		 */
+		dev_priv->rps.max_freq_softlimit =
+				data.task_state_data.freq_unslice_max;
+		dev_priv->rps.min_freq_softlimit =
+				data.task_state_data.freq_unslice_min;
+
+		dev_priv->rps.max_freq_softlimit *= GEN9_FREQ_SCALER;
+		dev_priv->rps.min_freq_softlimit *= GEN9_FREQ_SCALER;
+		dev_priv->guc.slpc.first_enable = true;
+	} else {
+		/* Ask SLPC to operate within min/max freq softlimits */
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv,
+					dev_priv->rps.max_freq_softlimit));
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv,
+					dev_priv->rps.max_freq_softlimit));
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv,
+					dev_priv->rps.min_freq_softlimit));
+		intel_slpc_set_param(dev_priv,
+				     SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+				     (u32) intel_gpu_freq(dev_priv,
+					dev_priv->rps.min_freq_softlimit));
+	}
 }
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index 8436965..9a8602a 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -189,6 +189,7 @@ struct slpc_shared_data {
 struct intel_slpc {
 	struct i915_vma *vma;
 	bool enabled;
+	bool first_enable;
 };
 
 /* intel_slpc.c */
-- 
1.9.1