[Intel-gfx] [PATCH] drm/i915 : Restore PWM_GRANULARITY after resume

[Lee, Shawn C]

From: "Lee, Shawn C" <shawn.c.lee at intel.com>

SPT_PWM_GRANULARITY (SOUTH_CHICKEN1, bit 0) controls the granularity
(minimum increment) of the PWM backlight control counter. PWM frequency
adjustment on 128 clock increments when this bit was 1. And 16 clock
increments when it was 0.

PWM frequency multiple octuple (from 200Hz to 1.6KHz) due to
SPT_PWM_GRANULARITY was clear to 0 after S3. This patch save
SOUTH_CHICKEN1 register value before suspend. And will restore
it after i915 resume.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97486

Cc: Jani Nikula <jani.nikula at intel.com>
Reviewed-by: Cooper Chiou <cooper.chiou at intel.com>
Reviewed-by: Wei Shun Chen <wei.shun.chang at intel.com>
Reviewed-by: Gary C Wang <gary.c.wang at intel.com>
Signed-off-by: Shawn Lee <shawn.c.lee at intel.com>
---
 drivers/gpu/drm/i915/intel_drv.h   |    1 +
 drivers/gpu/drm/i915/intel_panel.c |   21 +++++++++++++++++++--
 2 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 570a7ca..4c28692 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -256,6 +256,7 @@ struct intel_panel {
 		u32 level;
 		u32 min;
 		u32 max;
+		u32 pwm_granularity;
 		bool enabled;
 		bool combination_mode;	/* gen 2/4 only */
 		bool active_low_pwm;
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index c10e9b0..720fd5a 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -841,7 +841,17 @@ static void lpt_enable_backlight(struct intel_connector *connector)
 {
 	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	struct intel_panel *panel = &connector->panel;
-	u32 pch_ctl1, pch_ctl2;
+	u32 pch_ctl1, pch_ctl2, mul;
+
+	if (HAS_PCH_LPT(dev_priv)) {
+		mul = I915_READ(SOUTH_CHICKEN2);
+		mul &= ~LPT_PWM_GRANULARITY;
+		I915_WRITE(SOUTH_CHICKEN2, mul | panel->backlight.pwm_granularity);
+	} else {
+		mul = I915_READ(SOUTH_CHICKEN1);
+		mul &= ~SPT_PWM_GRANULARITY;
+		I915_WRITE(SOUTH_CHICKEN1, mul | panel->backlight.pwm_granularity);
+	}
 
 	pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1);
 	if (pch_ctl1 & BLM_PCH_PWM_ENABLE) {
@@ -1413,7 +1423,7 @@ static int lpt_setup_backlight(struct intel_connector *connector, enum pipe unus
 {
 	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	struct intel_panel *panel = &connector->panel;
-	u32 pch_ctl1, pch_ctl2, val;
+	u32 pch_ctl1, pch_ctl2, val, mul;
 
 	pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1);
 	panel->backlight.active_low_pwm = pch_ctl1 & BLM_PCH_POLARITY;
@@ -1421,6 +1431,13 @@ static int lpt_setup_backlight(struct intel_connector *connector, enum pipe unus
 	pch_ctl2 = I915_READ(BLC_PWM_PCH_CTL2);
 	panel->backlight.max = pch_ctl2 >> 16;
 
+	if (HAS_PCH_LPT(dev_priv))
+		mul = I915_READ(SOUTH_CHICKEN2) & LPT_PWM_GRANULARITY;
+	else
+		mul = I915_READ(SOUTH_CHICKEN1) & SPT_PWM_GRANULARITY;
+
+	panel->backlight.pwm_granularity = mul;
+
 	if (!panel->backlight.max)
 		panel->backlight.max = get_backlight_max_vbt(connector);
 
-- 
1.7.9.5