[Intel-gfx] [PATCH v8 03/12] drm: Helper to read max clock rate

[Ville Syrjälä]

On Wed, Aug 17, 2016 at 01:49:39PM +0300, Mika Kahola wrote:
> Helper routine to read out maximum supported pixel rate
> for DisplayPort legay VGA converter or TMDS clock rate
> for other digital legacy converters. The helper returns
> clock rate in kHz.
> 
> v2: Return early if detailed port cap info is not available.
>     Replace if-else ladder with switch-case (Ville)
> 
> Reviewed-by: Jim Bride <jim.bride at linux.intel.com>
> Signed-off-by: Mika Kahola <mika.kahola at intel.com>
> ---
>  drivers/gpu/drm/drm_dp_helper.c | 33 +++++++++++++++++++++++++++++++++
>  include/drm/drm_dp_helper.h     |  2 ++
>  2 files changed, 35 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index 031c4d3..7497490 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -439,6 +439,39 @@ int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link)
>  }
>  EXPORT_SYMBOL(drm_dp_link_configure);
>  
> +/**
> + * drm_dp_downstream_max_clock() - extract branch device max
> + *                                 pixel rate for legacy VGA
> + *                                 converter or max TMDS clock
> + *                                 rate for others
> + * @dpcd: DisplayPort configuration data
> + * @port_cap: port capabilities
> + *
> + * Returns max clock in kHz on success or 0 if max clock not defined
> + */
> +int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> +				const u8 port_cap[4])
> +{
> +	int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
> +	bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
> +		DP_DETAILED_CAP_INFO_AVAILABLE;
> +
> +	if (!detailed_cap_info)
> +		return 0;
> +
> +	switch (type) {
> +	case DP_DS_PORT_TYPE_VGA:
> +		return port_cap[1] * 8 * 1000;
> +	case DP_DS_PORT_TYPE_DVI:
> +	case DP_DS_PORT_TYPE_HDMI:
> +	case DP_DS_PORT_TYPE_DP_DUALMODE:
> +		return port_cap[1] * 2500;

The spec says that if the detailed_cap_info==0, then DVI/HDMI/DP++ must
support at least 165 MHz TMDS clock. I was thinking we might want to
limit things to 165 in that case to guarantee that we advertize only
modes guaranteed to work.

> +	default:
> +		return 0;
> +	}
> +}
> +EXPORT_SYMBOL(drm_dp_downstream_max_clock);
> +
>  /*
>   * I2C-over-AUX implementation
>   */
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 0d84046..60dd9dc 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -815,6 +815,8 @@ int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link);
>  int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link);
>  int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link);
>  int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link);
> +int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> +				const u8 port_cap[4]);
>  
>  void drm_dp_aux_init(struct drm_dp_aux *aux);
>  int drm_dp_aux_register(struct drm_dp_aux *aux);
> -- 
> 1.9.1

-- 
Ville Syrjälä
Intel OTC