[Intel-gfx] [PATCH v2 12/14] drm/i915: Remove the link rate and lane count loop in compute config

[Pandiyan, Dhinakaran]

On Thu, 2016-09-08 at 13:02 -0700, Manasi Navare wrote:
> While configuring the pipe during modeset, it should use
> max clock and max lane count and reduce the bpp until
> the requested mode rate is less than or equal to
> available link BW.
> This is required to pass DP Compliance.
> 
> v2:
> * Removed the loop since we use max values of clock
> and lane count (Dhinakaran Pandiyan)
> 
> Signed-off-by: Manasi Navare <manasi.d.navare at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 22 ++++++++--------------
>  1 file changed, 8 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 1378116..60c8857 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1567,20 +1567,14 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>  	for (; bpp >= 6*3; bpp -= 2*3) {
>  		mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
>  						   bpp);
> -
> -		for (clock = min_clock; clock <= max_clock; clock++) {
> -			for (lane_count = min_lane_count;
> -				lane_count <= max_lane_count;
> -				lane_count <<= 1) {
> -
> -				link_clock = common_rates[clock];
> -				link_avail = intel_dp_max_data_rate(link_clock,
> -								    lane_count);
> -
> -				if (mode_rate <= link_avail) {
> -					goto found;
> -				}
> -			}
> +		clock = max_clock;
> +		lane_count = max_lane_count;

Do we still need lane_count? We can eliminate it if it's always going to
be max_lane_count. 


> +		link_clock = common_rates[clock];

Same here for link_clock.

> +		link_avail = intel_dp_max_data_rate(link_clock,
> +						    lane_count);
> +
> +		if (mode_rate <= link_avail) {
> +			goto found;

Print KMS debug if we cannot satisfy the mode_rate at the max DP link
rate?

>  		}
>  	}
>