[Intel-gfx] [PATCH 2/2] drm/i915/execlists: Reset RING registers upon resume

[Joonas Lahtinen]

On pe, 2016-09-16 at 20:23 +0100, Chris Wilson wrote:
>  void intel_lr_context_resume(struct drm_i915_private *dev_priv)
>  {
> > -	struct i915_gem_context *ctx = dev_priv->kernel_context;
> >  	struct intel_engine_cs *engine;
> > +	struct i915_gem_context *ctx;
> +
> > +	/* Because we emit WA_TAIL_DWORDS there may be a disparity
> > +	 * between our bookkeeping in ce->ring->head and ce->ring->tail and
> +	 * that stored in context. As we only write new comamnds from

"new commands"

> +	 * ce->ring->tail onwards, everything before that is junk. If the GPU
> > +	 * starts reading from its RING_HEAD from the context, it may try to
> > +	 * execute that junk and die.
> > +	 *
> > +	 * So to avoid that we reset the context images upon resume. For
> > +	 * simplicity, we just zero everything out.
> > +	 */
> > +	list_for_each_entry(ctx, &dev_priv->context_list, link) {
> > +		for_each_engine(engine, dev_priv) {
> > +			struct intel_context *ce = &ctx->engine[engine->id];
> > +			u32 *reg_state;
>  
> > -	for_each_engine(engine, dev_priv) {
> > -		struct intel_context *ce = &ctx->engine[engine->id];
> > -		void *vaddr;
> > -		uint32_t *reg_state;
> -
> > -		if (!ce->state)
> > -			continue;
> -
> > -		vaddr = i915_gem_object_pin_map(ce->state->obj, I915_MAP_WB);
> > -		if (WARN_ON(IS_ERR(vaddr)))
> > -			continue;
> > +			if (!ce->state)
> > +				continue;
>  
> > -		reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
> > +			reg_state = i915_gem_object_pin_map(ce->state->obj,
> > +							    I915_MAP_WB);
> > +			if (WARN_ON(IS_ERR(reg_state)))
> > +				continue;
>  
> > -		reg_state[CTX_RING_HEAD+1] = 0;
> > -		reg_state[CTX_RING_TAIL+1] = 0;
> +			reg_state += LRC_STATE_PN * PAGE_SIZE / sizeof(u32);

/ sizeof(*reg_state) I presume.

Also add a newline here.

With those;

Reviewed-by: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>

Regards, Joonas
-- 
Joonas Lahtinen
Open Source Technology Center
Intel Corporation