[Intel-gfx] [PATCH 05/13] drm/i915: Sort forcewake mapping tables

[Chris Wilson]

On Thu, Sep 29, 2016 at 04:35:48PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
> 
> Sorting the tables (verified at runtime to help during
> development) is another prerequisite for interesting
> work which will follow.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_uncore.c | 55 ++++++++++++++++++++++++++++---------
>  1 file changed, 42 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index e21e65ab2a16..bee1482a5ece 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -605,16 +605,34 @@ find_fw_domain(u32 offset, const struct intel_forcewake_range *ranges,
>  	return -1;
>  }
>  
> +static void
> +intel_fw_table_check(const struct intel_forcewake_range *ranges,
> +		     unsigned int num_ranges)
> +{
> +	unsigned int i;
> +	struct intel_forcewake_range *entry =
> +		(struct intel_forcewake_range *)ranges;

Why the const cast away?

> +	s32 prev = -1;
> +
> +	for (i = 0; i < num_ranges; i++, entry++) {
> +		WARN_ON_ONCE(prev >= (s32)entry->start);
> +		prev = entry->start;
> +		WARN_ON_ONCE(prev >= (s32)entry->end);
> +		prev = entry->end;
> +	}

> +/* *Must* be sorted by offset ranges! */

/* *Must* be sorted by offset ranges! See intel_fw_table_check() */

>  static const struct intel_forcewake_range __vlv_fw_ranges[] = {
>  	GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
>  	GEN_FW_RANGE(0x5000, 0x7fff, FORCEWAKE_RENDER),
>  	GEN_FW_RANGE(0xb000, 0x11fff, FORCEWAKE_RENDER),
> -	GEN_FW_RANGE(0x2e000, 0x2ffff, FORCEWAKE_RENDER),
>  	GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
>  	GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_MEDIA),
> +	GEN_FW_RANGE(0x2e000, 0x2ffff, FORCEWAKE_RENDER),
>  	GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
>  };

Ok.

> @@ -660,23 +678,24 @@ static bool is_gen8_shadowed(u32 offset)
>  	__fwd; \
>  })
>  
> +/* *Must* be sorted by offset ranges! */
>  static const struct intel_forcewake_range __chv_fw_ranges[] = {
>  	GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
> +	GEN_FW_RANGE(0x4000, 0x4fff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
>  	GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
> +	GEN_FW_RANGE(0x8000, 0x82ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
>  	GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
> -	GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
> -	GEN_FW_RANGE(0xe000, 0xe7ff, FORCEWAKE_RENDER),
> +	GEN_FW_RANGE(0x8500, 0x85ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
>  	GEN_FW_RANGE(0x8800, 0x88ff, FORCEWAKE_MEDIA),
> +	GEN_FW_RANGE(0x9000, 0xafff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
> +	GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
>  	GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
> +	GEN_FW_RANGE(0xe000, 0xe7ff, FORCEWAKE_RENDER),
> +	GEN_FW_RANGE(0xf000, 0xffff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
>  	GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
>  	GEN_FW_RANGE(0x1a000, 0x1bfff, FORCEWAKE_MEDIA),
>  	GEN_FW_RANGE(0x1e800, 0x1e9ff, FORCEWAKE_MEDIA),
>  	GEN_FW_RANGE(0x30000, 0x37fff, FORCEWAKE_MEDIA),
> -	GEN_FW_RANGE(0x4000, 0x4fff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
> -	GEN_FW_RANGE(0x8000, 0x82ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
> -	GEN_FW_RANGE(0x8500, 0x85ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
> -	GEN_FW_RANGE(0x9000, 0xafff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
> -	GEN_FW_RANGE(0xf000, 0xffff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
>  };

Ok.

>  #define __chv_reg_read_fw_domains(offset) \
> @@ -703,23 +722,24 @@ static const struct intel_forcewake_range __chv_fw_ranges[] = {
>  	__fwd; \
>  })
>  
> +/* *Must* be sorted by offset ranges! */
>  static const struct intel_forcewake_range __gen9_fw_ranges[] = {
>  	GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
>  	GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
>  	GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
>  	GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
> +	GEN_FW_RANGE(0x8130, 0x813f, FORCEWAKE_MEDIA),
>  	GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
>  	GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
> +	GEN_FW_RANGE(0x8800, 0x89ff, FORCEWAKE_MEDIA),
>  	GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
> -	GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
> -	GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
> -	GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
>  	GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
> -	GEN_FW_RANGE(0x8130, 0x813f, FORCEWAKE_MEDIA),
> -	GEN_FW_RANGE(0x8800, 0x89ff, FORCEWAKE_MEDIA),
> +	GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
>  	GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
> +	GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
>  	GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
>  	GEN_FW_RANGE(0x1a000, 0x1e9ff, FORCEWAKE_MEDIA),
> +	GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
>  	GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
>  };

Ok.
  

-- 
Chris Wilson, Intel Open Source Technology Centre