[Intel-gfx] [PATCH 62/67] drm/i915/cnl: Add support slice/subslice/eu configs

[Rodrigo Vivi]

From: Ben Widawsky <ben at bwidawsk.net>

Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_drv.h          |  5 +++-
 drivers/gpu/drm/i915/i915_reg.h          | 21 +++++++++++++++
 drivers/gpu/drm/i915/intel_device_info.c | 45 +++++++++++++++++++++++++++++++-
 3 files changed, 69 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7dda202..fc787dd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -845,7 +845,10 @@ struct sseu_dev_info {
 	u8 slice_mask;
 	u8 subslice_mask;
 	u8 eu_total;
-	u8 eu_per_subslice;
+	union {
+		u8 per_subslice_eu_disable_mask[3][3];
+		u8 eu_per_subslice;
+	};
 	u8 min_eu_in_pool;
 	/* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
 	u8 subslice_7eu[3];
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b96de50..67f306e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2515,6 +2515,11 @@ enum skl_disp_power_wells {
 #define   GEN9_F2_SS_DIS_SHIFT		20
 #define   GEN9_F2_SS_DIS_MASK		(0xf << GEN9_F2_SS_DIS_SHIFT)
 
+#define   GEN10_F2_S_ENA_SHIFT		22
+#define   GEN10_F2_S_ENA_MASK		(0x7 << GEN10_F2_S_ENA_SHIFT)
+#define   GEN10_F2_SS_DIS_SHIFT		18
+#define   GEN10_F2_SS_DIS_MASK		(0x7 << GEN10_F2_SS_DIS_SHIFT)
+
 #define GEN8_EU_DISABLE0		_MMIO(0x9134)
 #define   GEN8_EU_DIS0_S0_MASK		0xffffff
 #define   GEN8_EU_DIS0_S1_SHIFT		24
@@ -2530,6 +2535,22 @@ enum skl_disp_power_wells {
 
 #define GEN9_EU_DISABLE(slice)		_MMIO(0x9134 + (slice)*0x4)
 
+#define GEN10_EU_DIS0_S0_SHIFT		0
+#define GEN10_EU_DIS0_S0_MASK		(0xff << GEN10_EU_DIS0_S0_SHIFT)
+#define GEN10_EU_DIS0_S1_SHIFT		8
+#define GEN10_EU_DIS0_S1_MASK		(0xff << GEN10_EU_DIS0_S1_SHIFT)
+#define GEN10_EU_DIS0_S2_SHIFT		16
+#define GEN10_EU_DIS0_S2_MASK		(0xff << GEN10_EU_DIS0_S2_SHIFT)
+#define GEN10_EU_DIS1_S0_SHIFT		24
+#define GEN10_EU_DIS1_S0_MASK		(0xff << GEN10_EU_DIS1_S0_SHIFT)
+#define GEN10_EU_DIS1_S1_SHIFT		0
+#define GEN10_EU_DIS1_S1_MASK		(0xff << GEN10_EU_DIS1_S1_SHIFT)
+#define GEN10_EU_DIS2_S0_SHIFT		8
+#define GEN10_EU_DIS2_S0_MASK		(0xff << GEN10_EU_DIS2_S0_SHIFT)
+#define GEN10_EU_DIS2_S1_SHIFT		16
+#define GEN10_EU_DIS2_S1_MASK		(0xff << GEN10_EU_DIS2_S1_SHIFT)
+/* Spec defines more, but they can't be valid */
+
 #define GEN6_BSD_SLEEP_PSMI_CONTROL	_MMIO(0x12050)
 #define   GEN6_BSD_SLEEP_MSG_DISABLE	(1 << 0)
 #define   GEN6_BSD_SLEEP_FLUSH_DISABLE	(1 << 2)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 5ae9a80..a2c59ab 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -81,6 +81,47 @@ void intel_device_info_dump(struct drm_i915_private *dev_priv)
 #undef PRINT_FLAG
 }
 
+static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
+{
+	struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
+	const u32 fuse2 = I915_READ(GEN8_FUSE2);
+	u32 temp, i, j;
+
+	sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >> GEN10_F2_S_ENA_SHIFT;
+	sseu->subslice_mask = (1 << 3) - 1;
+	sseu->subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
+				 GEN10_F2_SS_DIS_SHIFT);
+
+	temp = I915_READ(GEN8_EU_DISABLE0);
+	sseu->per_subslice_eu_disable_mask[0][0] =
+		(temp & GEN10_EU_DIS0_S0_MASK) >> GEN10_EU_DIS0_S0_SHIFT;
+	sseu->per_subslice_eu_disable_mask[0][1] =
+		(temp & GEN10_EU_DIS0_S1_MASK) >> GEN10_EU_DIS0_S1_SHIFT;
+	sseu->per_subslice_eu_disable_mask[0][2] =
+		(temp & GEN10_EU_DIS0_S2_MASK) >> GEN10_EU_DIS0_S2_SHIFT;
+	sseu->per_subslice_eu_disable_mask[1][0] =
+		(temp & GEN10_EU_DIS1_S0_MASK) >> GEN10_EU_DIS1_S0_SHIFT;
+
+	temp = I915_READ(GEN8_EU_DISABLE1);
+	sseu->per_subslice_eu_disable_mask[1][1] =
+		(temp & GEN10_EU_DIS1_S1_MASK) >> GEN10_EU_DIS1_S1_SHIFT;
+	sseu->per_subslice_eu_disable_mask[2][0] =
+		(temp & GEN10_EU_DIS2_S0_MASK) >> GEN10_EU_DIS2_S0_SHIFT;
+	sseu->per_subslice_eu_disable_mask[2][1] =
+		(temp & GEN10_EU_DIS2_S1_MASK) >> GEN10_EU_DIS2_S1_SHIFT;
+
+	for (i = 0; i < 3; i++)
+		for (j = 0; j < 3; j++)
+			sseu->eu_total +=
+				hweight8(~sseu->per_subslice_eu_disable_mask[i][j]);
+
+	/* On CNL, I cannot find any restrictions on power gating. */
+	sseu->has_slice_pg = 1;
+	sseu->has_subslice_pg = 1;
+	sseu->has_eu_pg = 1;
+}
+
+
 static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
 {
 	struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
@@ -408,8 +449,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 		cherryview_sseu_info_init(dev_priv);
 	else if (IS_BROADWELL(dev_priv))
 		broadwell_sseu_info_init(dev_priv);
-	else if (INTEL_INFO(dev_priv)->gen >= 9)
+	else if (INTEL_INFO(dev_priv)->gen == 9)
 		gen9_sseu_info_init(dev_priv);
+	else if (INTEL_INFO(dev_priv)->gen >= 10)
+		gen10_sseu_info_init(dev_priv);
 
 	info->has_snoop = !info->has_llc;
 
-- 
1.9.1