[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dp: rest of refactoring, link rate fallback (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/dp: rest of refactoring, link rate fallback (rev3)
URL   : https://patchwork.freedesktop.org/series/22586/
State : success

== Summary ==

Series 22586v3 drm/i915/dp: rest of refactoring, link rate fallback
https://patchwork.freedesktop.org/api/1.0/series/22586/revisions/3/mbox/

fi-bdw-5557u     total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  time: 432s
fi-bdw-gvtdvm    total:278  pass:256  dwarn:8   dfail:0   fail:0   skip:14  time: 425s
fi-bsw-n3050     total:278  pass:242  dwarn:0   dfail:0   fail:0   skip:36  time: 577s
fi-bxt-j4205     total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  time: 514s
fi-bxt-t5700     total:278  pass:258  dwarn:0   dfail:0   fail:0   skip:20  time: 541s
fi-byt-j1900     total:278  pass:254  dwarn:0   dfail:0   fail:0   skip:24  time: 486s
fi-byt-n2820     total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  time: 482s
fi-hsw-4770      total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  time: 408s
fi-hsw-4770r     total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  time: 405s
fi-ilk-650       total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  time: 424s
fi-ivb-3520m     total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time: 492s
fi-ivb-3770      total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time: 487s
fi-kbl-7500u     total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time: 452s
fi-kbl-7560u     total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  time: 567s
fi-skl-6260u     total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  time: 454s
fi-skl-6700hq    total:278  pass:261  dwarn:0   dfail:0   fail:0   skip:17  time: 567s
fi-skl-6700k     total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  time: 464s
fi-skl-6770hq    total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  time: 494s
fi-skl-gvtdvm    total:278  pass:265  dwarn:0   dfail:0   fail:0   skip:13  time: 429s
fi-snb-2520m     total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  time: 524s
fi-snb-2600      total:278  pass:249  dwarn:0   dfail:0   fail:0   skip:29  time: 401s

7aafd5c8395fea9a79fbee82de4ffc63c04790d6 drm-tip: 2017y-04m-06d-21h-02m-00s UTC integration manifest
d09e78a drm/i915: Implement Link Rate fallback on Link training failure
91e58a6 drm/i915/dp: Validate cached link rate and lane count before retraining
d49bedb drm/i915/dp: read sink count to a temporary variable first
c5150ed drm/i915/dp: use readb and writeb calls for single byte DPCD access
5f81a04 drm/i915/dp: localize link rate index variable more
f7874d5 drm/i915/mst: use max link not sink lane count
ffeaa33 drm/i915/dp: add functions for max common link rate and lane count
dd6ff8d drm/i915/dp: don't call the link parameters sink parameters
c6ffc38 drm/i915/dp: do not limit rate seek when not needed
f9d73b0 drm/i915/dp: cache common rates with sink rates
e45eeb8 drm/i915/dp: use the sink rates array for max sink rates

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4431/