[Intel-gfx] [PATCH 1/3] dma-fence: Reserve 0 as a special NO_CONTEXT token

Christian König christian.koenig at amd.com
Sun Apr 9 18:00:44 UTC 2017


Am 09.04.2017 um 18:02 schrieb Chris Wilson:
> On Sun, Apr 09, 2017 at 09:08:53AM +0200, Christian König wrote:
>> Am 08.04.2017 um 20:00 schrieb Chris Wilson:
>>> On Sat, Apr 08, 2017 at 07:49:37PM +0200, Christian König wrote:
>>>> Am 08.04.2017 um 18:26 schrieb Chris Wilson:
>>>>> Reserve 0 for general use a token meaning that the fence doesn't belong
>>>>> to an ordered timeline (fence context).
>>>> NAK, we kept context allocation cheap to avoid exactly that.
>>> However, they result in very sparse mappings.
>> Which is perfectly fine at least for how we use this in Radeon and Amdgpu.
>>
>> The fence context is used as key for a hashtable, even when the
>> context is only used once we want an evenly distribution over all of
>> them.
> The ht is a more expensive solution.

Not when the fences without contexts are rare.

>>>> Please elaborate further why it should be necessary now.
>>> Because I want to efficiently exclude them from comparisons as
>>> demonstrated by this small series as there may be several hundred such
>>> fences as dependencies for this job.
>> That would horrible break Amdgpu, Radeon and the GPU scheduler
>> because all of them assume that context numbers are unique.
> Why would it break if it respected the trivial notion of an unordered
> timeline?

You seem to miss the point. We already had that discussion and decided 
against using no-context fences.

Now we have a whole bunch of cases over different drivers/components 
where we assume uniqueness of fence contexts.

If you change this without fixing all those cases they will just subtle 
break, probably without anybody noticing the problem immediately.

So if you don't want to scan all drivers for such cases (and I know at 
least three of hand) and fix them before that patch then that is a clear 
no-go for this patch.

I suggest to just use two separate fence contexts for you clflush 
problem in i915. We have a similar situation in the GPU scheduler solve 
it the same way.

Regards,
Christian.

> -Chris
>



More information about the Intel-gfx mailing list