[Intel-gfx] [PATCH 05/67] drm/i915/cnp: add CNP gmbus support

[Srivatsa, Anusha]

>-----Original Message-----
>From: Intel-gfx [mailto:intel-gfx-bounces at lists.freedesktop.org] On Behalf Of
>Rodrigo Vivi
>Sent: Thursday, April 6, 2017 12:15 PM
>To: intel-gfx at lists.freedesktop.org
>Cc: Nikula, Jani <jani.nikula at intel.com>; Vetter, Daniel
><daniel.vetter at intel.com>; Vivi, Rodrigo <rodrigo.vivi at intel.com>
>Subject: [Intel-gfx] [PATCH 05/67] drm/i915/cnp: add CNP gmbus support
>
>On CNP PCH based platforms the gmbus is on the south display that is on PCH.
>The existing implementation for previous platforms already covers the need for
>CNP expect for the pin pair configuration that follows similar definitions that we
>had on BXT.
>
>v2: Don't drop "_BXT" as the indicator of the first platform
>    supporting this pin numbers. Suggested by Daniel.
>v3: Add missing else and fix register table since CNP GPIO_CTL
>    starts on 0xC5014.
>v4: Fix pin number and map according to the current available VBT.
>    Re-add pin 4 for port D. Lost during some rebase.
>
>Cc: Daniel Vetter <daniel.vetter at intel.com>
>Cc: Jani Nikula <jani.nikula at intel.com>
>Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa at intel.com>

> drivers/gpu/drm/i915/i915_reg.h   |  3 ++-
> drivers/gpu/drm/i915/intel_hdmi.c |  8 +++++---
>drivers/gpu/drm/i915/intel_i2c.c  | 20 ++++++++++++++++++--
> 3 files changed, 25 insertions(+), 6 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 6826547..efbbeb8 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -2618,9 +2618,10 @@ enum skl_disp_power_wells {
> #define   GMBUS_PIN_DPB		5 /* SDVO, HDMIB */
> #define   GMBUS_PIN_DPD		6 /* HDMID */
> #define   GMBUS_PIN_RESERVED	7 /* 7 reserved */
>-#define   GMBUS_PIN_1_BXT	1
>+#define   GMBUS_PIN_1_BXT	1 /* BXT+ (atom) and CNP+ (big core) */
> #define   GMBUS_PIN_2_BXT	2
> #define   GMBUS_PIN_3_BXT	3
>+#define   GMBUS_PIN_4_CNP	4
> #define   GMBUS_NUM_PINS	7 /* including 0 */
> #define GMBUS1			_MMIO(dev_priv->gpio_mmio_base +
>0x5104) /* command/status */
> #define   GMBUS_SW_CLR_INT	(1<<31)
>diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
>b/drivers/gpu/drm/i915/intel_hdmi.c
>index 6efc3cb..f8c40ae 100644
>--- a/drivers/gpu/drm/i915/intel_hdmi.c
>+++ b/drivers/gpu/drm/i915/intel_hdmi.c
>@@ -1892,19 +1892,21 @@ static u8 intel_hdmi_ddc_pin(struct
>drm_i915_private *dev_priv,
>
> 	switch (port) {
> 	case PORT_B:
>-		if (IS_GEN9_LP(dev_priv))
>+		if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
> 			ddc_pin = GMBUS_PIN_1_BXT;
> 		else
> 			ddc_pin = GMBUS_PIN_DPB;
> 		break;
> 	case PORT_C:
>-		if (IS_GEN9_LP(dev_priv))
>+		if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
> 			ddc_pin = GMBUS_PIN_2_BXT;
> 		else
> 			ddc_pin = GMBUS_PIN_DPC;
> 		break;
> 	case PORT_D:
>-		if (IS_CHERRYVIEW(dev_priv))
>+		if (HAS_PCH_CNP(dev_priv))
>+			ddc_pin = GMBUS_PIN_4_CNP;
>+		else if (IS_CHERRYVIEW(dev_priv))
> 			ddc_pin = GMBUS_PIN_DPD_CHV;
> 		else
> 			ddc_pin = GMBUS_PIN_DPD;
>diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
>index b6401e8..d7eabab 100644
>--- a/drivers/gpu/drm/i915/intel_i2c.c
>+++ b/drivers/gpu/drm/i915/intel_i2c.c
>@@ -68,11 +68,25 @@ struct gmbus_pin {
> 	[GMBUS_PIN_3_BXT] = { "misc", GPIOD },  };
>
>+/*
>+ * FIXME: Spec maps 3-misc-0xc541c and 4-portd-0xc5420.
>+ * However, current available pre-prod VBT maps:
>+ * portD to pin 3 using 0xc5420.
>+*/
>+static const struct gmbus_pin gmbus_pins_cnp[] = {
>+	[GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
>+	[GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
>+	[GMBUS_PIN_3_BXT] = { "misc", GPIOE },
>+	[GMBUS_PIN_4_CNP] = { "dpd", GPIOD },
>+};
>+
> /* pin is expected to be valid */
> static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private
>*dev_priv,
> 					     unsigned int pin)
> {
>-	if (IS_GEN9_LP(dev_priv))
>+	if (HAS_PCH_CNP(dev_priv))
>+		return &gmbus_pins_cnp[pin];
>+	else if (IS_GEN9_LP(dev_priv))
> 		return &gmbus_pins_bxt[pin];
> 	else if (IS_GEN9_BC(dev_priv))
> 		return &gmbus_pins_skl[pin];
>@@ -87,7 +101,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private
>*dev_priv,  {
> 	unsigned int size;
>
>-	if (IS_GEN9_LP(dev_priv))
>+	if (HAS_PCH_CNP(dev_priv))
>+		size = ARRAY_SIZE(gmbus_pins_cnp);
>+	else if (IS_GEN9_LP(dev_priv))
> 		size = ARRAY_SIZE(gmbus_pins_bxt);
> 	else if (IS_GEN9_BC(dev_priv))
> 		size = ARRAY_SIZE(gmbus_pins_skl);
>--
>1.9.1
>
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