[Intel-gfx] [PATCH 1/4] drm/i915: Differentiate between sw write location into ring and last hw read

[Chris Wilson]

On Mon, Apr 24, 2017 at 03:21:56PM +0300, Mika Kuoppala wrote:
> Chris Wilson <chris at chris-wilson.co.uk> writes:
> 
> > We need to keep track of the last location we ask the hw to read up to
> > (RING_TAIL) separately from our last write location into the ring, so
> > that in the event of a GPU reset we do not tell the HW to proceed into
> > a partially written request (which can happen if that request is waiting
> > for an external signal before being executed).
> 
> But is it so that this can happen also without external signal?
> Our submit is already async and waiting for the prev. And we have
> already pushed the tail into the partial 'current'.

You need something to delay the request submission. In gem_exec_fence,
it is waiting on a request from another engine (that happens to be a
deliberate hang). Similarly, any third party signal would leave the
request incomplete whilst we continue to write new requests after it.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre