[Intel-gfx] [PATCH 58/67] drm/i915/cnl: Cannonlake color init.

[Ville Syrjälä]

On Thu, Apr 06, 2017 at 12:15:54PM -0700, Rodrigo Vivi wrote:
> Cannonlake has same color setup as Geminilake.
> Legacy color load luts doesn't work anymore on Cannonlake+.

Not sure what that means. The legacy 8bpc LUT i no longer there?
The code still depends on that working, and we also still expose the C8
format which at least used to depend on the legacy LUT.

> 
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_pci.c      | 1 +
>  drivers/gpu/drm/i915/intel_color.c   | 2 +-
>  drivers/gpu/drm/i915/intel_display.c | 4 ++--
>  drivers/gpu/drm/i915/intel_sprite.c  | 2 +-
>  4 files changed, 5 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index bace848..1e8e0ac 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -438,6 +438,7 @@
>  	.gen = 10,
>  	.ddb_size = 1024,
>  	.has_csr = 1,
> +	.color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
>  };
>  
>  /*
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index 306c6b0..f85d575 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -615,7 +615,7 @@ void intel_color_init(struct drm_crtc *crtc)
>  		   IS_BROXTON(dev_priv)) {
>  		dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
>  		dev_priv->display.load_luts = broadwell_load_luts;
> -	} else if (IS_GEMINILAKE(dev_priv)) {
> +	} else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
>  		dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
>  		dev_priv->display.load_luts = glk_load_luts;
>  	} else {
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 3adee22..697c112 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3302,7 +3302,7 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
>  
>  	plane_ctl = PLANE_CTL_ENABLE;
>  
> -	if (!IS_GEMINILAKE(dev_priv)) {
> +	if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(dev_priv)) {
>  		plane_ctl |=
>  			PLANE_CTL_PIPE_GAMMA_ENABLE |
>  			PLANE_CTL_PIPE_CSC_ENABLE |
> @@ -3359,7 +3359,7 @@ static void skylake_update_primary_plane(struct drm_plane *plane,
>  
>  	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>  
> -	if (IS_GEMINILAKE(dev_priv)) {
> +	if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
>  		I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
>  			      PLANE_COLOR_PIPE_GAMMA_ENABLE |
>  			      PLANE_COLOR_PIPE_CSC_ENABLE |
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index f7d4314..a002c1a 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -240,7 +240,7 @@ void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work
>  
>  	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>  
> -	if (IS_GEMINILAKE(dev_priv)) {
> +	if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
>  		I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
>  			      PLANE_COLOR_PIPE_GAMMA_ENABLE |
>  			      PLANE_COLOR_PIPE_CSC_ENABLE |
> -- 
> 1.9.1
> 
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-- 
Ville Syrjälä
Intel OTC