[Intel-gfx] [PATCH i-g-t 18/29] igt/perf: print [un]slice freq and report reasons in debug

[Lionel Landwerlin]

From: Robert Bragg <robert at sixbynine.org>

Signed-off-by: Robert Bragg <robert at sixbynine.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
---
 tests/perf.c | 58 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 57 insertions(+), 1 deletion(-)

diff --git a/tests/perf.c b/tests/perf.c
index 08ee8665..ab8db296 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -428,6 +428,28 @@ gen8_read_report_ticks(uint32_t *report, enum drm_i915_oa_format format)
 	return report[3];
 }
 
+static const char *
+gen8_read_report_reason(const uint32_t *report)
+{
+	uint32_t reason = ((report[0] >> OAREPORT_REASON_SHIFT) &
+			   OAREPORT_REASON_MASK);
+
+	if (reason & (1<<0))
+		return "timer";
+	else if (reason & (1<<1))
+	      return "internal trigger 1";
+	else if (reason & (1<<2))
+	      return "internal trigger 2";
+	else if (reason & (1<<3))
+	      return "context switch";
+	else if (reason & (1<<4))
+	      return "GO 1->0 transition (enter RC6)";
+	else if (reason & (1<<5))
+		return "[un]slice clock ratio change";
+	else
+		return "unknown";
+}
+
 static uint64_t
 timebase_scale(uint32_t u32_delta)
 {
@@ -749,7 +771,7 @@ init_sys_info(void)
 				test_set_uuid = "882fa433-1f4a-4a67-a962-c741888fe5f5";
 				break;
 			default:
-				igt_debug("unsupport Skylake GT size\n");
+				igt_debug("unsupported Skylake GT size\n");
 				return false;
 			}
 			timestamp_frequency = 12000000;
@@ -1159,6 +1181,20 @@ open_and_read_2_oa_reports(int format_id,
 }
 
 static void
+gen8_read_report_clock_ratios(uint32_t *report,
+			      uint32_t *slice_freq_mhz,
+			      uint32_t *unslice_freq_mhz)
+{
+	uint32_t unslice_freq = report[0] & 0x1ff;
+	uint32_t slice_freq_low = (report[0] >> 25) & 0x7f;
+	uint32_t slice_freq_high = (report[0] >> 9) & 0x3;
+	uint32_t slice_freq = slice_freq_low | (slice_freq_high << 7);
+
+	*slice_freq_mhz = (slice_freq * 16666) / 1000;
+	*unslice_freq_mhz = (unslice_freq * 16666) / 1000;
+}
+
+static void
 print_reports(uint32_t *oa_report0, uint32_t *oa_report1, int fmt)
 {
 	igt_debug("TIMESTAMP: 1st = %"PRIu32", 2nd = %"PRIu32", delta = %"PRIu32"\n",
@@ -1174,6 +1210,26 @@ print_reports(uint32_t *oa_report0, uint32_t *oa_report1, int fmt)
 			  clock0, clock1, clock1 - clock0);
 	}
 
+	if (intel_gen(devid) >= 8) {
+		uint32_t slice_freq0, slice_freq1, unslice_freq0, unslice_freq1;
+		const char *reason0 = gen8_read_report_reason(oa_report0);
+		const char *reason1 = gen8_read_report_reason(oa_report1);
+
+		gen8_read_report_clock_ratios(oa_report0,
+					      &slice_freq0, &unslice_freq0);
+		gen8_read_report_clock_ratios(oa_report1,
+					      &slice_freq1, &unslice_freq1);
+
+		igt_debug("SLICE CLK: 1st = %umhz, 2nd = %umhz, delta = %d\n",
+			  slice_freq0, slice_freq1,
+			  ((int)slice_freq1 - (int)slice_freq0));
+		igt_debug("UNSLICE CLK: 1st = %umhz, 2nd = %umhz, delta = %d\n",
+			  unslice_freq0, unslice_freq1,
+			  ((int)unslice_freq1 - (int)unslice_freq0));
+
+		igt_debug("REASONS: 1st = \"%s\", 2nd = \"%s\"\n", reason0, reason1);
+	}
+
 	/* Gen8+ has some 40bit A counters... */
 	for (int j = 0; j < oa_formats[fmt].n_a40; j++) {
 		uint64_t value0 = gen8_read_40bit_a_counter(oa_report0, fmt, j);
-- 
2.11.0