[Intel-gfx] [PATCH v10] drm/i915: Squash repeated awaits on the same fence
Tvrtko Ursulin
tvrtko.ursulin at linux.intel.com
Fri Apr 28 09:55:09 UTC 2017
On 28/04/2017 08:41, Chris Wilson wrote:
[snip]
> +static int igt_sync(void *arg)
> +{
> + const struct {
> + const char *name;
> + u32 seqno;
> + bool expected;
> + bool set;
> + } pass[] = {
> + { "unset", 0, false, false },
> + { "new", 0, false, true },
> + { "0a", 0, true, true },
> + { "1a", 1, false, true },
> + { "1b", 1, true, true },
> + { "0b", 0, true, false },
> + { "2a", 2, false, true },
> + { "4", 4, false, true },
> + { "INT_MAX", INT_MAX, false, true },
> + { "INT_MAX-1", INT_MAX-1, true, false },
> + { "INT_MAX+1", (u32)INT_MAX+1, false, true },
> + { "INT_MAX", INT_MAX, true, false },
> + { "UINT_MAX", UINT_MAX, false, true },
> + { "wrap", 0, false, true },
> + { "unwrap", UINT_MAX, true, false },
> + {},
> + }, *p;
> + struct intel_timeline *tl;
> + int order, offset;
> + int ret;
> +
> + tl = mock_timeline(0);
> + if (!tl)
> + return -ENOMEM;
> +
> + for (p = pass; p->name; p++) {
> + for (order = 1; order < 64; order++) {
> + for (offset = -1; offset <= (order > 1); offset++) {
> + u64 ctx = BIT_ULL(order) + offset;
> +
> + if (__intel_timeline_sync_is_later
> + (tl, ctx, p->seqno) != p->expected) {
> + pr_err("1: %s(ctx=%llu, seqno=%u) expected passed %s but failed\n",
> + p->name, ctx, p->seqno, yesno(p->expected));
> + ret = -EINVAL;
> + goto out;
> + }
> +
> + if (p->set) {
> + ret = __intel_timeline_sync_set(tl, ctx, p->seqno);
> + if (ret)
> + goto out;
> + }
> + }
> + }
> + }
I think verification that the tree height matches the expectation, and
also total number of nodes, is required.
If too complicated in the current structure you could add a simpler
iteration over another table of steps, which would include the ctx id
and seqno in it, and expected height/total nodes after each step.
Regards,
Tvrtko
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