[Intel-gfx] [PATCH] drm/i915: enable WaDisableDopClkGating for gen9

[Rodrigo Vivi]

On Wed, Aug 2, 2017 at 10:34 AM, Praveen Paneri
<praveen.paneri at intel.com> wrote:
> This WA is required when decoupled frequencies for slice and unslice
> are enabled. This disables DOP clock gating for gen9.
>
> v2: enable the WA for all gen9 platforms (not just for SKL GT4 where
>     the hang issue is originally reported) to avoid rare hangs (David)
>
> Cc: David Weinehall <david.weinehall at linux.intel.com>
> Reviewed-by: David Weinehall <david.weinehall at linux.intel.com>
> Signed-off-by: Praveen Paneri <praveen.paneri at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 3fc42aa..e369d77 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -88,6 +88,12 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
>         /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */
>         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
>                    ILK_DPFC_DISABLE_DUMMY0);
> +
> +       if (IS_GEN9(dev_priv)) {

I believe we should go with IS_SKYLAKE(dev_priv)

Bspec only list this Wa for:
BDW: ALL
CHV: UNTIL A7

WaDatabase only list this to:
SKL: SIWA_FOREVER
BDW: SIWA_FOREVER
CHV: SIWA_CHV_UNTIL_A7
SNB: SIWA_UNTIL_GT_MOBILE_D0

> +               /* WaDisableDopClockGating */
> +               I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL)
> +                          & ~GEN7_DOP_CLOCK_GATE_ENABLE);
> +       }
>  }
>
>  static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
> --
> 1.9.1
>
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-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br