[Intel-gfx] [PATCH v3] drm/i915: enable WaDisableDopClkGating for skl

[Praveen Paneri]

This WA is required when decoupled frequencies for slice and unslice
are enabled. This disables DOP clock gating for skl.

v2: enable the WA for all gen9 platforms (not just for SKL GT4 where
    the hang issue is originally reported) to avoid rare hangs (David)
v3: as per WaDatabase, enable it only for SKL (Rodrigo)

Cc: David Weinehall <david.weinehall at linux.intel.com>
Reviewed-by: David Weinehall <david.weinehall at linux.intel.com>
Signed-off-by: Praveen Paneri <praveen.paneri at intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3fc42aa..1c6bc08 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -60,7 +60,7 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
 {
 	u32 misccpctl;
 
-	if (IS_SKL_GT4(dev_priv))
+	if (IS_SKYLAKE(dev_priv))
 	{
 		/* WaTempDisableDOPClkGating: */
 		misccpctl = I915_READ(GEN7_MISCCPCTL);
@@ -88,6 +88,12 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
 	/* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */
 	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
 		   ILK_DPFC_DISABLE_DUMMY0);
+
+	if (IS_GEN9(dev_priv)) {
+		/* WaDisableDopClockGating */
+		I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL)
+			   & ~GEN7_DOP_CLOCK_GATE_ENABLE);
+	}
 }
 
 static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
-- 
1.9.1