[Intel-gfx] [PATCH v2 08/16] drm/i915/guc: Update CT message header definition

[Daniele Ceraolo Spurio]

On 07/08/17 09:14, Michal Wajdeczko wrote:
> Flags bits are different in G2H message.
> 
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko at intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
> Cc: Oscar Mateo <oscar.mateo at intel.com>
> Cc: Kelvin Gardiner <kelvin.gardiner at intel.com>

Matches GuC defines, so:

Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>

-Daniele

> ---
>   drivers/gpu/drm/i915/intel_guc_fwif.h | 11 +++++++++--
>   1 file changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
> index 367aa65..89781d3 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> @@ -358,17 +358,24 @@ struct guc_ct_buffer_desc {
>    *
>    * bit[4..0]	message len (in dwords)
>    * bit[7..5]	reserved
> + * bit[10..8]	flags
> + * bit[15..11]	reserved
> + * bit[31..16]	action code
> + *
> + * H2G flags:
>    * bit[8]	write fence to desc
>    * bit[9]	write status to H2G buff
>    * bit[10]	send status (via G2H)
> - * bit[15..11]	reserved
> - * bit[31..16]	action code
> + *
> + * G2H flags:
> + * bit[8]	is response
>    */
>   #define GUC_CT_MSG_LEN_SHIFT			0
>   #define GUC_CT_MSG_LEN_MASK			0x1F
>   #define GUC_CT_MSG_WRITE_FENCE_TO_DESC		(1 << 8)
>   #define GUC_CT_MSG_WRITE_STATUS_TO_BUFF		(1 << 9)
>   #define GUC_CT_MSG_SEND_STATUS			(1 << 10)
> +#define GUC_CT_MSG_IS_RESPONSE			(1 << 8)
>   #define GUC_CT_MSG_ACTION_SHIFT			16
>   #define GUC_CT_MSG_ACTION_MASK			0xFFFF
>   
>