[Intel-gfx] [PATCH 1/3] drm/i915/cnl: Add allowed DP rates for Cannonlake.

[Mika Kahola]

On Thu, 2017-07-06 at 13:54 -0700, Rodrigo Vivi wrote:
> One warning is that in order to get DPLL Link rates
> 3240 and 4050 that allows 648000 and 810000 is that:
> "Some SKUs may require elevated I/O voltage to support
> this."
I also found a mention in BSpec 

"Frequencies over 5.4 GHz only supported on certain DDI ports and SKUs"

The only difference between SKUs that I spotted was related to DDI D
port speeds. If BSpec is correct, then we should somehow separate the
max port speeds for DDI D port.

> 
> v2: Rebase on top of source_rates changes.
> 
> Cc: Clint Taylor <clinton.a.taylor at intel.com>
> Cc: Mika Kahola <mika.kahola at intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c
> b/drivers/gpu/drm/i915/intel_dp.c
> index 2d42d09..4355bdf 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -97,6 +97,9 @@ struct dp_link_dpll {
>  				  324000, 432000, 540000 };
>  static const int skl_rates[] = { 162000, 216000, 270000,
>  				  324000, 432000, 540000 };
> +static const int cnl_rates[] = { 162000, 216000, 270000,
> +				 324000, 432000, 540000,
> +				 648000, 810000 };
>  static const int default_rates[] = { 162000, 270000, 540000 };
>  
>  /**
> @@ -238,6 +241,9 @@ int intel_dp_max_lane_count(struct intel_dp
> *intel_dp)
>  	if (IS_GEN9_LP(dev_priv)) {
>  		source_rates = bxt_rates;
>  		size = ARRAY_SIZE(bxt_rates);
> +	} else if (IS_CANNONLAKE(dev_priv)) {
> +		source_rates = cnl_rates;
> +		size = ARRAY_SIZE(cnl_rates);
>  	} else if (IS_GEN9_BC(dev_priv)) {
>  		source_rates = skl_rates;
>  		size = ARRAY_SIZE(skl_rates);
-- 
Mika Kahola - Intel OTC