[Intel-gfx] [PATCH 5/6] drm/i915/gen10: implement gen 10 watermarks calculations

[Mahesh Kumar]

Hi,


On Thursday 10 August 2017 02:22 AM, Rodrigo Vivi wrote:
> From: Paulo Zanoni <paulo.r.zanoni at intel.com>
>
> They're slightly different than the gen 9 calculations.
>
> v2: Remove TODO comment. Code matches recent spec.
>
> Cc: Mahesh Kumar <mahesh1.kumar at intel.com>
> Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
> ---
>   drivers/gpu/drm/i915/intel_pm.c | 21 +++++++++++++++------
>   1 file changed, 15 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 1622e6f3c6b6..857e2f0a4b15 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4274,8 +4274,9 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
>    * should allow pixel_rate up to ~2 GHz which seems sufficient since max
>    * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
>   */
> -static uint_fixed_16_16_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp,
> -					 uint32_t latency)
> +static uint_fixed_16_16_t
> +skl_wm_method1(const struct drm_i915_private *dev_priv, uint32_t pixel_rate,
> +	       uint8_t cpp, uint32_t latency)
>   {
>   	uint32_t wm_intermediate_val;
>   	uint_fixed_16_16_t ret;
> @@ -4285,6 +4286,10 @@ static uint_fixed_16_16_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp,
>   
>   	wm_intermediate_val = latency * pixel_rate * cpp;
>   	ret = div_fixed16(wm_intermediate_val, 1000 * 512);
> +
> +	if (INTEL_GEN(dev_priv) >= 10)
> +		ret.val += 1 << 16;
Please use available fp16.16 wrapper to add
        ret = add_fixed16_u32(ret, 1);
> +
>   	return ret;
>   }
>   
> @@ -4436,11 +4441,15 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
>   
>   	plane_bytes_per_line = width * cpp;
>   	if (y_tiled) {
> -		interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line *
> -					   y_min_scanlines, 512);
> +		interm_pbpl = plane_bytes_per_line * y_min_scanlines;
> +
> +		if (INTEL_GEN(dev_priv) >= 10)
> +			interm_pbpl++;
> +
> +		interm_pbpl = DIV_ROUND_UP(interm_pbpl, 512);
It looks wrong, my interpretation of Bspec is:
             interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line * 
y_min_scanlines, 512);
                  if (INTEL_GEN(dev_priv) >= 10)
                         interm_pbpl++;

-Mahesh
>   		plane_blocks_per_line = div_fixed16(interm_pbpl,
>   							y_min_scanlines);
> -	} else if (x_tiled) {
> +	} else if (x_tiled && INTEL_GEN(dev_priv) == 9) {
>   		interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line, 512);
>   		plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
>   	} else {
> @@ -4448,7 +4457,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
>   		plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
>   	}
>   
> -	method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
> +	method1 = skl_wm_method1(dev_priv, plane_pixel_rate, cpp, latency);
>   	method2 = skl_wm_method2(plane_pixel_rate,
>   				 cstate->base.adjusted_mode.crtc_htotal,
>   				 latency,